LM3S1607 Luminary Micro, Inc, LM3S1607 Datasheet - Page 18

• Manufacturer Part Number: LM3S1607
• Description: Lm3s1607 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
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Inter-Integrated Circuit (I
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SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 441
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 442
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 443
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 444
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 445
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 446
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 447
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 448
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 449
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 450
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 451
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 452
I
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C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 467
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 468
C Master Data (I2CMDR), offset 0x008 ......................................................................... 472
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 473
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 474
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 475
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 476
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 477
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 478
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 480
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 481
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 483
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 484
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 485
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 486
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 487
2
C) Interface ........................................................................................ 453
Preliminary
June 02, 2008