XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 68

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

CLB Arithmetic Switching Characteristics
Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment
listed. Precise values are provided by the timing analyzer.
DS001-3 (v2.7) September 3, 2003
Product Specification
Notes:
1.
Combinatorial Delays
Multiplier Operation
Setup/Hold Times with Respect to Clock CLK
T
T
CCKX
CCKY
A zero hold time listing indicates no hold time or a negative hold time.
T
T
T
T
Symbol
T
T
T
T
T
T
T
T
T
T
GANDCY
GANDYB
T
T
FANDXB
FANDYB
FANDCY
T
T
OPGYB
OPCYG
OPCYF
T
CINXB
CINYB
OPXB
OPYB
OPGY
BXCY
CINX
CINY
OPX
OPY
BYP
/ T
/ T
R
CKCX
CKCY
F operand inputs to X via XOR
F operand input to XB output
F operand input to Y via XOR
F operand input to YB output
F operand input to COUT output
G operand inputs to Y via XOR
G operand input to YB output
G operand input to COUT output
BX initialization input to COUT
CIN input to X output via XOR
CIN input to XB
CIN input to Y via XOR
CIN input to YB
CIN input to COUT output
F1/2 operand inputs to XB output via AND
F1/2 operand inputs to YB output via AND
F1/2 operand inputs to COUT output via AND
G1/2 operand inputs to YB output via AND
G1/2 operand inputs to COUT output via AND
CIN input to FFX
CIN input to FFY
Description
(1)
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Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
1.1 / 0
1.2 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
Max
Speed Grade
0.8
1.3
1.7
1.7
1.3
0.9
1.6
1.2
0.9
0.4
0.1
0.5
0.6
0.1
0.5
0.9
0.5
0.6
0.2
-
-
1.2 / 0
1.3 / 0
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
Max
0.9
1.5
2.0
2.0
1.5
1.1
2.0
1.4
1.0
0.5
0.1
0.6
0.7
0.1
0.5
1.1
0.6
0.7
0.2
-
-
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15