XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 18

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the netlist for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
static timing analyzer.
For in-circuit debugging, the development system includes
a download and readback cable, which connects the FPGA
in the target system to a PC or workstation. After download-
ing the design into the FPGA, the designer can single-step
the logic, readback the contents of the flip-flops, and so
observe the internal logic state. Simple modifications can
be downloaded into the system in a matter of minutes.
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx development software, is
loaded into the internal configuration memory of the FPGA.
Spartan-II devices support both serial configuration, using
the master/slave serial and JTAG modes, as well as
byte-wide configuration employing the Slave Parallel mode.
Configuration File
Spartan-II devices are configured by sequentially loading
frames of data that have been concatenated into a configu-
ration file.
space is needed for Spartan-II devices.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of differ-
ent kinds of under populated nonvolatile storage already
available either on or off the board (i.e., hard drives, FLASH
Table 8: Configuration Modes
DS001-2 (v2.2) September 3, 2003
Product Specification
Notes:
1.
Master Serial mode
Slave Parallel mode
Boundary-Scan mode
Slave Serial mode
Configuration Mode
After power-on, the I/O drivers will be in a high-impedance state. After configuration, all unused I/Os (those not assigned signals) will
remain in a high-impedance state.
Table 7
R
shows how much nonvolatile storage
Preconfiguration
Pull-ups
Yes
Yes
Yes
Yes
No
No
No
No
M0
0
0
0
0
1
1
1
1
www.xilinx.com
1-800-255-7778
M1
0
0
1
1
0
0
1
1
cards, etc.) can be used. For more information on configu-
ration without a PROM, refer to XAPP098, The Low-Cost,
Efficient Serial Configuration of Spartan FPGAs.
Table 7: Spartan-II Configuration File Size
Modes
Spartan-II devices support the following four configuration
modes:
•
•
•
•
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
configuration. The selection codes are listed in
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
M2
0
1
0
1
0
1
0
1
Spartan-II 2.5V FPGA Family: Functional Description
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
Direction
CCLK
N/A
Out
In
In
Configuration File Size (Bits)
Data Width
1
8
1
1
1,040,096
1,335,840
197,696
336,768
559,200
781,216
Serial D
Module 2 of 4
Table
Yes
Yes
No
No
OUT
8.
11