XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 31

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: Functional Description
could alternatively be implemented using similar connec-
tions.
Because any single DLL can only access at most two
BUFGs, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
Generating a 4x Clock
By connecting two DLL circuits each implementing a 2x
clock multiplier in series as shown in
multiply can be implemented with zero ns skew between
registers in the same device.
If other clock output is needed, the clock could access a
BUFG only if the DLLs are constrained to exist on opposite
edges (Top or Bottom) of the device.
When using this circuit it is vital to use the SRL16 cell to
reset the second DLL after the initial chip reset. If this is not
done, the second DLL may not recognize the change of fre-
quencies from when the input changes from a 1x (25/75)
waveform to a 2x (50/50) waveform.
Using Block RAM Features
The Spartan-II FPGA family provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block RAM memory
can be independently configured as a read/write port, a
read port, a write port, and can be configured to a specific
data width. The block RAM memory offers new capabilities
allowing the FPGA designer to simplify designs.
Operating Modes
Block RAM memory supports two operating modes.
•
•
Read Through (One Clock Edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories may place the latch/register at the outputs
depending on the desire to have a faster clock-to-out versus
Module 2 of 4
24
Figure 28: DLL Deskew of Clock and 2x Multiple
Read Through
Write Back
IBUFG
IBUF
CLKIN
CLKFB
RST
CLKDLL
LOCKED
CLK180
CLK270
CLKDV
CLK2X
CLK90
CLK0
Figure
BUFG
BUFG
OBUF
DS001_29_061200
29, a 4x clock
www.xilinx.com
1-800-255-7778
setup time. This is generally considered to be an inferior
solution since it changes the read operation to an asynchro-
nous function with the possibility of missing an address/con-
trol line transition during the generation of the read pulse
clock.
Write Back (One Clock Edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the write port input.
Block RAM Characteristics
1. All inputs are registered with the port clock and have a
2. All outputs have a read through or write back function
3. The block RAM are true SRAM memories and do not
4. The ports are completely independent from each other
setup to clock timing specification.
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
have a combinatorial path from the address to the
output. The LUT cells in the CLBs are still available with
this function.
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
IBUFG
Figure 29: DLL Generation of 4x Clock
RST
RST
CLKIN
CLKFB
CLKIN
CLKFB
CLKDLL
CLKDLL
LOCKED
LOCKED
CLK180
CLK270
CLK180
CLK270
CLKDV
CLKDV
CLK2X
CLK2X
CLK90
CLK90
CLK0
CLK0
DS001-2 (v2.2) September 3, 2003
BUFG
BUFG
OBUF
Product Specification
D
A3
A2
A1
A0
SRL16
WCLK
DS001_30_061200
Q
INV
R