XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 57

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
Module 3 of 4
4
Notes:
1.
2.
Notes:
1.
2.
3.
4.
Notes:
1.
2.
3.
CTT
AGP
Input/Output
Standard
V
Tested according to the relevant specifications.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
Methodology, page
DLL output jitter is already included in the timing calculation.
For data output with different standards, adjust delays with the values shown in
Standards, page
Global Clock Input Adjustments, page
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables
Methodology, page
For data output with different standards, adjust delays with the values shown in
Standards, page
Global Clock Input Adjustments, page
T
OL
Symbol
Symbol
ICKOFDLL
T
ICKOF
and V
OH
for lower drive currents are sample tested.
V, Min
–0.5
–0.5
9. For a global clock input with standards other than LVTTL, adjust delays with values from the
9. For a global clock input with standards other than LVTTL, adjust delays with values from the
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, with DLL.
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, without DLL.
10.
10.
V
IL
V
V
REF
REF
V, Max
Description
Description
– 0.2
– 0.2
11.
11.
V
V
REF
REF
V, Min
+ 0.2
+ 0.2
www.xilinx.com
1-800-255-7778
V
Constants for Calculating T
Constants for Calculating T
IH
XC2S100
XC2S150
XC2S200
XC2S15
XC2S30
XC2S50
Device
V, Max
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-II devices unless otherwise noted.
3.6
3.6
Device
All
V
10% V
REF
V, Max
IOB Output Delay Adjustments for Different
IOB Output Delay Adjustments for Different
V
Min
All
OL
– 0.4
CCO
Min
All
IOOP
IOOP
Speed Grade
(1)
Speed Grade
V
90% V
and
and
REF
Max
V, Min
4.5
4.5
4.5
4.6
4.6
4.7
DS001-3 (v2.7) September 3, 2003
-6
V
(1)
Max
OH
Delay Measurement
Delay Measurement
2.9
-6
+ 0.4
CCO
Product Specification
Note (2)
Max
Max
5.4
5.4
5.4
5.5
5.5
5.6
3.3
-5
-5
mA
I
OL
8
I/O Standard
I/O Standard
Note (2)
Units
Units
ns
mA
ns
ns
ns
ns
ns
ns
I
–8
OH
R