XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 66

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Product Specification
Notes:
1.
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Clock CLK
Sequential Delays
Setup Times with Respect to Clock CLK
Clock CLK
T
T
T
T
T
T
A zero hold time listing indicates no hold time or a negative hold time.
T
Symbol
Symbol
WS
SHCKO16
SHCKO32
DS
AS
T
SHCECK
T
T
SHDICK
T
T
T
SRPH
SRPL
WPH
WPL
REG
WC
/ T
/ T
/ T
AH
DH
WH
R
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
Minimum pulse width, High
Minimum pulse width, Low
Minimum clock period to meet address write cycle time
Clock CLK to X/Y outputs
BX/BY data inputs (DIN)
CE input (WS)
Minimum pulse width, High
Minimum pulse width, Low
Description
Description
(1)
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Spartan-II FPGA Family: DC and Switching Characteristics
0.7 / 0
0.8 / 0
0.9 / 0
Min
Min
0.8
0.9
-
-
-
-
-
-
-
-
-6
-6
Max
Max
3.47
Speed Grade
Speed Grade
2.2
2.5
2.9
2.9
5.8
2.9
2.9
-
-
-
-
-
0.7 / 0
0.9 / 0
1.0 / 0
Min
Min
0.9
1.0
-
-
-
-
-
-
-
-
-5
-5
Max
Max
3.88
2.6
3.0
2.9
2.9
5.8
2.9
2.9
-
-
-
-
-
Module 3 of 4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66