XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 15

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

Figure 9
logic. It includes three bits of Data Register per IOB, the
IEEE 1149.1 Test Access Port controller, and the Instruction
Register with decodes.
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins
contributes all three bits.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in
BSDL (Boundary Scan Description Language) files for
Spartan-II family devices are available on the Xilinx
website, in the
DS001-2 (v2.8) June 13, 2008
Product Specification
TDI
IOB
IOB
IOB
IOB
IOB
IOB
IOB
is a diagram of the Spartan-II family boundary scan
R
Downloads
IOB
Instruction Register
IOB
Register
Bypass
IOB
area.
IOB
Figure 9: Spartan-II Family Boundary Scan Logic
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
M
U
X
Figure
TDO
www.xilinx.com
10.
IOB.Q
IOB.T
IOB.T
IOB.I
IOB.I
CAPTURE
SHIFT/
DATAOUT
DATA IN
CLOCK DATA
REGISTER
1
0
1
0
Spartan-II FPGA Family: Functional Description
1
0
1
0
1
0
D
D
D
D
D
Q
Q
Q
Q
Q
UPDATE
D
D
D
D
D
LE
LE
LE
LE
LE
sd
sd
sd
sd
sd
Q
Q
Q
Q
Q
0
1
1
0
1
0
0
1
1
0
EXTEST
Module 2 of 4
DS001_09_032300
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