XC2S100E-7PQ208C Xilinx, Inc., XC2S100E-7PQ208C Datasheet - Page 45

• Manufacturer Part Number: XC2S100E-7PQ208C
• Description: 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
• Manufacturer: Xilinx, Inc.

HSTL Class III
A sample circuit illustrating a valid termination technique for
HSTL_III appears in
appear in
Specifications"
characteristics.
Table 23: HSTL Class III Voltage Specification
DS001-2 (v2.8) June 13, 2008
Product Specification
Notes:
1.
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
Parameter
Per EIA/JESD8-6, "The value of V
user to provide optimum noise margin in the use conditions
specified by the user."
at V
HSTL Class III
at V
(1)
V
CCO
OL
OH
Figure 45: Terminated HSTL Class III
Table 23
(mA)
R
= 1.5V
(mA)
in Module 3 for the actual FPGA
for the HSTL_III standard. See
Figure
V
V
CCO
REF
1.40
Min
–8
24
-
-
-
-
Z = 50
+ 0.1
– 0.4
45. DC voltage specifications
V
REF
REF
= 0.9V
50Ω
V
V
1.50
0.90
Typ
is to be selected by the
TT
CCO
-
-
-
-
-
-
= 1.5V
DS001_45_061200
V
REF
"DC
Max
1.60
0.4
-
-
-
-
-
-
– 0.1
www.xilinx.com
HSTL Class IV
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in
appear in
Specifications"
characteristics
Table 24: HSTL Class IV Voltage Specification
Notes:
1.
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
Parameter
Per EIA/JESD8-6, "The value of V
user to provide optimum noise margin in the use conditions
specified by the user."
at V
HSTL Class IV
at V
V
Spartan-II FPGA Family: Functional Description
CCO
OL
OH
Figure 46: Terminated HSTL Class IV
Table 23
(mA)
= 1.5V
(mA)
in Module 3 for the actual FPGA
50Ω
V
for the HSTL_IV standard. See
TT
V
V
Figure
CCO
REF
= 1.5V
1.40
Min
–8
48
-
-
-
-
+ 0.1
– 0.4
46.DC voltage specifications
Z = 50
V
REF
REF
V
1.50
0.90
Typ
= 0.9V
50Ω
CCO
V
-
-
-
-
-
-
is to be selected by the
TT
= 1.5V
DS001_46_061200
V
Module 2 of 4
REF
Max
1.60
0.4
"DC
-
-
-
-
-
-
– 0.1
45