IDT72V281L15PF IDT, Integrated Device Technology Inc, IDT72V281L15PF Datasheet - Page 24

• Manufacturer Part Number: IDT72V281L15PF
• Description: IC FIFO 32768X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V281L15PF

• Function: Synchronous
• Memory Size: 589K (32K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V281L15PF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/
OR assertion to vary by one cycle between FIFOs. In IDT Standard mode,
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
greater than 65,536 and 131,072 for the IDT72V291 with a 9-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of
one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 22 shows
a depth expansion using two IDT72V281/72V291 devices.
FIFOs in the depth expansion configuration. The first word written to an
empty configuration will pass from one FIFO to the next ("ripple down") until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
The IDT72V281 can easily be adapted to applications requiring depths
Care should be taken to select FWFT mode during Master Reset for all
For an empty expansion configuration, the amount of time it takes for OR
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
TM
72V281
72V291
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
24
0
n
- Qm
such problems can be avoided by creating composite flags, that is, ANDing
EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT
mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing IR of every FIFO.
72V291 devices. D
Q
be attained by adding additional IDT72V281/72V291 devices.
FIFO's outputs) after a word has been written to the first FIFO is the sum of the
delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
0
The "ripple down" delay is only noticeable for the first word written to an
The first free location created by reading from a full depth expansion
-Q
Figure 21 demonstrates a width expansion using two IDT72V281/
72V281
72V291
8
FIFO
from each device form a 18-bit wide output bus. Any word width can
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
0
Qm
- D
(N – 1)*(4*transfer clock) + 3*T
8
+1
from each device form a 18-bit wide input bus and
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
RCLK
RCLK
is the RCLK period.
4513 drw 24
GATE
SKEW3
(1)