IDT72V281L15PF IDT, Integrated Device Technology Inc, IDT72V281L15PF Datasheet - Page 10

• Manufacturer Part Number: IDT72V281L15PF
• Description: IC FIFO 32768X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V281L15PF

• Function: Synchronous
• Memory Size: 589K (32K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 64Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V281L15PF

SERIAL PROGRAMMING MODE
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: when LD and SEN are set LOW, data on
the SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits
for the IDT72V281 and 34 bits for the IDT72V291. See Figure 13, Serial
Loading of Programmable Flag Registers, for the timing diagram for this
mode.
selectively. PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written to
the SI input and then, by bringing LD and SEN HIGH, data can be written
to FIFO memory via D
with LD and SEN restored to a LOW, the next offset bit in sequence is
written to the registers via SI. If an interruption of serial programming is
desired, it is sufficient either to set LD LOW and deactivate SEN or to set
SEN LOW and deactivate LD. Once LD and SEN are both restored to
a LOW level, serial offset programming continues.
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus t
PAE will be valid after the next two rising RCLK edges plus t
t
PARALLEL MODE
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and D
IDT72V281, programming PAE and PAF proceeds as follows: when LD
and WEN are set LOW, data on the inputs Dn are written into the Empty
Offset LSB Register on the first LOW-to-HIGH transition of WCLK. Upon the
second LOW-to-HIGH transition of WCLK, data are written into the Empty
Offset MSB Register. Upon the third LOW-to-HIGH transition of WCLK,
data are written into the Full Offset LSB Register. Upon the fourth LOW-
to-HIGH transition of WCLK, data are written into the Full Offset MSB
Register. The fifth transition of WCLK writes, once again, to the Empty
Offset LSB Register. See Figure 14, Parallel Loading of Programmable
Flag Registers for the IDT72V281, for the timing diagram for this mode.
follows: when LD and WEN are set LOW, data on the inputs D
into the Empty Offset LSB Register on the first LOW-to-HIGH transition of
WCLK. Upon the second LOW-to-HIGH transition of WCLK, data are
written into the Empty Offset Mid-Byte Register. Upon the third LOW-to-
HIGH transition of WCLK, data are written into the Empty Offset MSB
Register. Upon the fourth LOW-to-HIGH transition of WCLK, data are
written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Mid-Byte Register.
SKEW2
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
If Serial Programming mode has been selected, as described above,
Using the serial method, individual registers cannot be programmed
Write operations to the FIFO are allowed before and during the serial
From the time serial programming has begun, neither partial flag will be
It is not possible to read the flag offset values in a serial mode.
If Parallel Programming mode has been selected, as described above,
For the IDT72V291, programming PAE and PAF proceeds as
.
n
by toggling WEN. When WEN is brought HIGH
n
input pins. For the
TM
n
are written
PAE
PAF
plus
,
10
Upon the sixth LOW-to-HIGH transition of WCLK, data are written into the
Full Offset MSB Register. The seventh transition of WCLK writes, once
again, into the Empty Offset LSB Register. See Figure 15, Parallel Loading
of Programmable Flag Registers for the IDT72V291, for the timing diagram
for this mode.
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers.
A Master Reset initializes both pointers to the Empty Offset (LSB) register.
A Partial Reset has no effect on the position of these pointers.
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can
be written and then by bringing LD HIGH, write operations can be
redirected to the FIFO memory. When LD is set LOW again, and WEN is
LOW, the next offset register in sequence is written to. As an alternative to
holding WEN LOW and toggling LD, parallel programming can also be
interrupted by setting LD LOW and toggling WEN.
during the programming process. From the time parallel programming has
begun, a partial flag output will not be valid until the appropriate offset word
has been written to the register(s) pertaining to that flag. Measuring from the
rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus t
rising RCLK edges plus t
register pointer. The contents of the offset registers can be read on the Q
Q
data are read via Q
to-HIGH transition of RCLK. Upon the second LOW-to-HIGH transition of
RCLK, data are read from the Empty Offset MSB Register. Upon the third
LOW-to-HIGH transition of RCLK, data are read from the Full Offset LSB
Register. Upon the fourth LOW-to-HIGH transition of RCLK, data are read
from the Full Offset MSB Register. The fifth transition of RCLK reads, once
again, from the Empty Offset LSB Register. See Figure 16, Parallel Read
of Programmable Flag Registers for the IDT72V281, for the timing diagram
for this mode.
Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read from the Empty Offset Mid-
Byte Register. Upon the third LOW-to-HIGH transition of RCLK, data are
read from the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH
transition of RCLK, data are read from the Full Offset LSB Register. Upon
the fifth LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Mid-Byte Register. Upon the sixth LOW-to-HIGH transition of RCLK, data
are read from the Full Offset MSB Register. The seventh transition of RCLK
reads, once again, from the Empty Offset LSB Register. See Figure 17,
Parallel Read of Programmable Flag Registers for the IDT72V291, for the
timing diagram for this mode.
or writes to the FIFO. The interruption is accomplished by deasserting
REN, LD, or both together. When REN and LD are restored to a LOW
level, reading of the offset registers continues where it left off. It should be
noted, and care should be taken from the fact that when a parallel read of
the flag offsets is performed, the data word that was present on the output
lines Qn will be overwritten.
n
pins when LD is set LOW and REN is set LOW. For the IDT72V281,
The act of writing offsets in parallel employs a dedicated write offset
Write operations to the FIFO are allowed before and during the parallel
Note that the status of a partial flag (PAE or PAF) output is invalid
The act of reading the offset registers employs a dedicated read offset
For the IDT72V291, data is read via Q
It is permissible to interrupt the offset register read sequence with reads
n
from the Empty Offset LSB Register on the first LOW-
PAE
plus t
PAF
SKEW2
, PAE will be valid after the next two
COMMERCIAL AND INDUSTRIAL
.
n
from the Empty Offset LSB
TEMPERATURE RANGES
0
-