IDT72271LA15TF IDT, Integrated Device Technology Inc, IDT72271LA15TF Datasheet - Page 17

• Manufacturer Part Number: IDT72271LA15TF
• Description: IC FIFO 16384X18 LP 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72271LA15TF

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 32Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72271LA15TF

NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
Q
D
NOTES:
1. t
2. LD = HIGH.
3. First word latency: 60ns + t
D
Q
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
WCLK
RCLK
0
0
WEN
WCLK
0
0
rising edge of the RCLK and the rising edge of the WCLK is less than t
RCLK
REN
edge of WCLK and the rising edge of RCLK is less than t
SKEW1
- Q
- D
WEN
SKEW3
REN
OE
- D
- Q
EF
n
n
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
OLZ
t
t
ENH
SKEW1
t
REF
t
A
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
REF
OE
(1)
+ 1*T
t
SKEW3
t
t
ENS
ENH
RCLK.
t
DS
t
A
D
(1)
1
0
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO WRITE
NO OPERATION
t
t
DHS
ENH
LAST WORD
1
SKEW3
2
t
, then EF deassertion may be delayed one extra RCLK cycle.
WFF
t
OHZ
t
SKEW1
t
t
DS
DS
ENS
, then the FF deassertion may be delayed one extra WCLK cycle.
D
1
D
NO OPERATION
X
t
CLKH
t
WFF
t
t
ENH
DH
DATA READ
17
t
DH
t
CLK
2
t
CLKL
t
CLKH
t
REF
t
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
REF
). If the time between the rising
NEXT DATA READ
t
ENS
t
WFF
t
DS
JANUARY 7, 2009
D
0
D
X
+1
t
REF
t
t
ENH
A
4671 drw 10
t
DH
t
4671 drw 11
WFF
D
1