IDT723631L15PF IDT, Integrated Device Technology Inc, IDT723631L15PF Datasheet - Page 19

• Manufacturer Part Number: IDT723631L15PF
• Description: IC FIFO SYNC 512X36 120-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723631L15PF

• Function: Synchronous
• Memory Size: 18.4K (512 x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723631L15PF

NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. Retransmit feature is not supported in depth expansion applications.
4. The amount of time it takes for OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
5. The amount of time is takes for IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
B0 - B35
V
A0 - A35
CC
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*
(N - 1)*(3*transfer clock) + 2*T
CLKB
CLKA
W/RB
MBF2
W/RA
MBB
CSA
MBA
CSB
ENB
ENA
DATA IN (Dn)
WRITE
ALMOST-FULL FLAG (AF)
WRITE CLOCK (CLKA)
WRITE ENABLE (ENA)
WRITE SELECT (W/RA)
CHIP SELECT (CSA)
A
INPUT READY (IR)
0
-A
35
n
Figure 17. Block Diagram of 512 x 36, 1,024 x 36, 2,048 x 36 Synchronous FIFO Memory with
MBA
WCLK
, where N is the number of FIFOs in the expansion and T
t
t
t
ENS2
t
ENS2
ENS2
ENS2
t
EN
723631
723641
723651
Programmable Flags used in Depth Expansion Configuration
IDT
t
DS
W1
Figure 16. Timing for Mail2
t
t
t
t
ENH2
ENH2
ENH2
t
DH
ENH2
t
PMF
t
PMR
W/RB
OR
ENB
CSB
B
Qn
CLKB
MBB
0
-B
35
TRANSFER CLOCK
TRCLK
V
Mail2
Mail2 Register and MBF2
Mail2
Mail2
CC
, where N is the number of FIFOs in the expansion and T
19
n
V
CC
W1 (Remains valid in Mail2 Register after read)
A
CLKA
W/RA
0
MBA
ENA
CSA
-A
WCLK
Dn
IR
35
is the CLKA period.
MBF2
MBF2
MBF2 Flag
MBF2
t
ENS1
723631
723641
723651
IDT
t
ENH1
t
PMF
COMMERCIAL AND INDUSTRIAL
MBB
READ CLOCK (CLKB)
CHIP SELECT (CSB)
OUTPUT READY (OR)
READ ENABLE (ENB)
ALMOST-EMPTY FLAG (AE)
READ SELECT (W/RB)
n
TEMPERATURE RANGES
RCLK
B
DATA OUT (Qn)
0
-B
t
DIS
is the CLKB period.
35
3023 drw19
READ
3023 drw20
V
CC