IDT723631L15PF IDT, Integrated Device Technology Inc, IDT723631L15PF Datasheet - Page 10

• Manufacturer Part Number: IDT723631L15PF
• Description: IC FIFO SYNC 512X36 120-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723631L15PF

• Function: Synchronous
• Memory Size: 18.4K (512 x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723631L15PF

when CLKA and CLKB operate asynchronously to one another. OR and
AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of words stored
in memory.
OUTPUT READY FLAG (OR)
reads data from its array (CLKB). When the OR flag is HIGH, new data is
present in the FIFO output register. When the OR flag is LOW, the previ-
ous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
its output register. The state machine that controls an OR flag monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAM status is empty, empty+1, or empty+2. From the time a word is
written to a FIFO, it can be shifted to the FIFO output register in a minimum
of three cycles of CLKB. Therefore, an OR flag is LOW if a word in
memory is the next data to be sent to the FIFO output register and three
CLKB cycles have not elapsed since the time the word was written. The
OR flag of the FIFO remains LOW until the third LOW-to-HIGH transition of
CLKB occurs, simultaneously forcing the OR flag HIGH and shifting the
word to the FIFO output register.
of a write if the clock transition occurs at time tSKEW1 or greater after the
write. Otherwise, the subsequent CLKB cycle may be the first synchroniza-
tion cycle (see Figure 7).
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
The Output Ready flag of a FIFO is synchronized to the port Clock that
A FIFO read pointer is incremented each time a new word is clocked to
A LOW-to-HIGH transition on CLKB begins the first synchronization cycle
CSA
CSB
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W/RB
W/RA
H
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
ENA
ENB
H
H
H
H
H
H
H
H
X
L
L
L
X
L
L
L
MBA
MBB
H
H
H
H
H
H
X
X
L
L
L
X
X
L
L
L
CLKA
CLKB
X
X
↑
↑
X
↑
X
↑
X
X
↑
↑
X
↑
X
↑
Active, FIFO Output Register
Active, FIFO Output Register
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail1 Register
Active, Mail1 Register
10
A0-A35 Outputs
B0-A35 Outputs
INPUT READY FLAG (IR)
writes data to its array (CLKA). When the IR flag is HIGH, a memory
location is free in the SRAM to write new data. No memory locations are
free when the IR flag is LOW and attempted writes to the FIFO are ignored.
The state machine that controls an IR flag monitors a write-pointer and
read pointer comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from a FIFO, its previous
memory location is ready to be written in a minimum of three cycles of
CLKA. Therefore, an IR flag is LOW if less than two cycles of CLKA have
elapsed since the next memory write location has been read. The second
LOW-to-HIGH transition on CLKA after the read sets the Input Ready flag
HIGH, and data can be written in the following cycle.
of a read if the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent CLKA cycle may be the first synchroniza-
tion cycle (see Figure 8).
ALMOST-EMPTY FLAG (AE)
reads data from its array (CLKB). The state machine that controls an AE
flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-
empty+2. The almost-empty state is defined by the contents of register X.
This register is loaded with a preset value during a FIFO reset, pro-
The Input Ready flag of a FIFO is synchronized to the port Clock that
Each time a word is written to a FIFO, its write pointer is incremented.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
The Almost-Empty flag of a FIFO is synchronized to the port Clock that
COMMERCIAL AND INDUSTRIAL
Mail2 Read (Set MBF2 HIGH)
Mail1 Read (Set MBF1 HIGH)
Port Functions
Port Functions
TEMPERATURE RANGES
FIFO Write
Mail1 Write
Mail2 Write
FIFO read
None
None
None
None
None
None
None
None
None
None