AD8343 Analog Devices, AD8343 Datasheet - Page 14

• Manufacturer Part Number: AD8343
• Description: DC-to-2.5 GHz High IP3 Active Mixer
• Manufacturer: Analog Devices

AD8343
INPUT INTERFACE (INPP AND INPM)
Single-Ended-to-Differential Conversion
The AD8343 is designed to accept differential input signals for
best performance. While a single-ended input can be applied,
the signal capacity is reduced by 6 dB. Further, there would be
no cancellation of even-order distortion arising from the nonlin-
ear input impedances, so the effective signal handling capacity
will be reduced even further in distortion-sensitive situations.
That is, the intermodulation intercepts are degraded.
For these reasons it is strongly recommended that differential
signals be presented to the AD8343’s input. In addition to com-
mercially available baluns, there are various discrete and printed
circuit elements that can produce the required balanced wave-
forms and impedance match (i.e., rat-race baluns). These
alternate circuits can be employed to further reduce the compo-
nent cost of the mixer.
Baluns implemented in transmission line form (also known as
common-mode chokes) are useful up to frequencies of around
1 GHz, but are often excessively lossy at the highest frequencies
that the AD8343 can handle. M/A-Com manufactures these
baluns with their ETC line. Murata produces a true surface-
mount balun with their LDB20C series. Coilcraft and Toko are
also manufacturers of RF baluns.
Input Matching Considerations
The design of the input matching network should be undertaken
with two goals in mind: matching the source impedance to the
input impedance of the AD8343 and providing a dc bias current
path for the bias setting resistors.
TO-DIFFERENTIAL
LO INPUT SIGNAL
SINGLE-ENDED-
SINGLE-ENDED
CONVERSION
DCPL
PWDN
LOIM
LOIP
VPOS
CELL
BIAS
DRIVER
LO
COMM
CORE BIAS NETWORK
TO-DIFFERENTIAL
INPUT MATCHING
SINGLE-ENDED-
SINGLE-ENDED
CONVERSION
INPUT SIGNAL
NETWORK
INPP
AD8343
INPM
CORE
OUTM
OUTP
OUTPUT MATCHING
OUTPUT SIGNAL
SINGLE-ENDED
DIFFERENTIAL-
SINGLE-ENDED
CONVERSION
CORE BIAS
NETWORK
NETWORK
TO-
The maximum power transfer into the device will occur when
there is a conjugate impedance match between the signal source
and the input of the AD8343. This match can be achieved with
the differential equivalent of the classic “L” network, as illustrated
in Figure 8. The figure gives two examples of the transformation
from a single-ended “L” network to its differential counterpart.
The design of “L” matching networks is adequately covered in
texts on RF amplifier design (for example: “Microwave Transis-
tor Amplifiers” by Guillermo Gonzalez).
Figure 9 shows the differential input impedance of the AD8343
at the pins of the device. The two measurements shown in the
figure are for two different core currents set by resistors R3 and
R4; the real value impedance shift is caused by the change in tran-
sistor r
files are available at the ADI web site (www.analog.com).
Figure 9 provides a reasonable starting point for the design of
the network. However, the particular board traces and pads will
transform the input impedance at frequencies in excess of about
500 MHz. For this reason it is best to make a differential input
impedance measurement at the board location where the match-
ing network will be installed, as a starting point for designing an
accurate matching network.
Differential impedance measurement is made relatively easy
through the use of a technique presented in an article by Lutz
Konstroffer in RF Design, January 1999, entitled “Finding the
Reflection Coefficient of a Differential One-Port Device.” This
article presents a mathematical formula for converting from a
two-port single-ended measurement to differential impedance.
A full two-port measurement is performed using a vector network
analyzer with Port 1 and Port 2 connected to the two differential
inputs of the device at the desired measurement plane. The two-
port measurement results are then processed with Konstroffer’s
formula (following), which is straightforward and can be imple-
mented through most RF design packages that can read and
analyze network analyzer data.
E
due to the change in current. The standard S parameter
SINGLE-ENDED
68
L1
L2
50MHz
500MHz
C2
1000MHz
FREQUENCY (50MHz – 2500MHz)
1500MHz
134
C1
2500MHz
DIFFERENTIAL
L1/2
L1/2
L2
2C2
2C2
C1