AD8343 Analog Devices, AD8343 Datasheet - Page 13

• Manufacturer Part Number: AD8343
• Description: DC-to-2.5 GHz High IP3 Active Mixer
• Manufacturer: Analog Devices

DC INTERFACES
Biasing and Decoupling (VPOS, DCPL)
VPOS is the power supply connection for the internal bias cir-
cuit and the LO driver. This pin should be closely bypassed to
GND with a capacitor in the range of 0.01 µF to 0.1 µF. The
DCPL pin provides access to an internal bias node for noise
bypassing purposes. This node should be bypassed to COMM
with 0.1 µF.
Power-Down Interface (PWDN)
The AD8343 is active when the PWDN pin is held low; other-
wise the device enters a low-power state as shown in Figure 3.
To assure full power-down, the PWDN voltage should be within
0.5 V of the supply voltage at VPOS. Normal operation requires
that the PWDN pin be taken at least 1.5 V below the supply
voltage. The PWDN pin sources about 100 µA when pulled to
GND (refer to Pin Function Descriptions). It is not advisable to
leave the pin floating when the device is to be disabled; a resis-
tive pull-up to VPOS is the minimum suggestion.
The AD8343 requires about 2.5 µs to turn OFF when PWDN is
asserted; turn ON time is about 500 ns. Figures 4 and 5 show
typical characteristics (they will vary with bypass component
values). Figure 6 shows the test configuration used to acquire
these waveforms.
45
40
35
30
25
20
15
10
1
2
5
0
3.0
CH1
200nV
3.5
CH2
PWDN VOLTAGE – Volts
1.00V
4.0
M 500ns CH2
PWDN SWEPT
FROM BOTH
3V TO 5V
5V TO 3V
4.5
AND
4.48V
5.0
AC INTERFACES
Because of the AD8343’s wideband design, there are several
points to consider in its ac implementation; the Basic AC
Signal Connection diagram shown in Figure 7 summarizes
these points. The input signal undergoes a single-ended-to-
differential conversion and is then reactively matched to the
impedance presented by the emitters of the core. The matching
network also provides bias currents to these emitters. Similarly,
the LO input undergoes a single-ended-to-differential transfor-
mation before it is applied to the 50 Ω differential LO port. The
differential output signal currents appear at high-impedance
collectors and may be reactively matched and converted to a
single-ended signal.
VPOS
TRANSFORMER
NETWORK AND
GENERATOR
GENERATOR
1
2
MATCHING
HP8648C
SIGNAL
HP8130
PULSE
CH1
1nH
RF INPUT
1740MHz
200nV
TRIGGER
0.1 F
0.1 F
CH2
1
2
3
4
5
6
7
OSCILLOSCOPE
COMM
INPP
INPM
DCPL
VPOS
PWDN
COMM
TEKTRONIX
1.00V
TDS694C
AD8343
COMM
COMM
COMM
OUTM
OUTP
LOIM
LOIP
M 100ns CH2
14
13
12
11
10
9
8
IF OUTPUT
170MHz
TRANSFORMER
TRANSFORMER
NETWORK AND
AD8343
GENERATOR
MATCHING
HP8648C
SIGNAL
4.48V
LO INPUT
1570MHz