IDT72V825L15PF IDT, Integrated Device Technology Inc, IDT72V825L15PF Datasheet - Page 9

• Manufacturer Part Number: IDT72V825L15PF
• Description: IC SYNCFIFO 1024X18X2 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V825L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V825L15PF

SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D17)
CONTROLS:
RESET (RSA/RSB)
a LOW state. During reset, both internal read and write pointers are set to
the first location. A reset is required after power-up before a write operation
can take place. The Half-Full flag (HFA/HFB) and Programmable Almost-
Full flag (PAFA/PAFB) will be reset to HIGH after t
Almost-Empty flag (PAEA/PAEB) will be reset to LOW after t
Flag (FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset
to LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During
reset, the output register is initialized to all zeros and the offset registers
are initialized to their default values.
WRITE CLOCK (WCLKA/WCLKB)
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
WRITE ENABLE (WENA/WENB)
FIFO RAM array on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
WCLK cycle.
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF flag is updated on
the rising edge of WCLK.
go HIGH, inhibiting further write operations. Upon the completion of a valid
read cycle, IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
mode.
READ CLOCK (RCLKA/RCLKB)
Read Clock (RCLKA/RCLKB), when Output Enable (OEA/OEB) is set
LOW.
READ ENABLE (RENA/RENB)
array into the output register on the rising edge of every RCLK cycle if the
device is not empty.
and no new data is loaded into the output register. The data outputs Q0-
Qn maintain the previous data value.
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Data inputs for 18-bit wide data.
Reset is accomplished whenever the Reset (RSA/RSB) input is taken to
A write cycle is initiated on the LOW-to-HIGH transition of the Write
The Write and Read Clocks can be asynchronous or coincident.
When the WENA/WENB input is LOW, data may be loaded into the
When WEN is HIGH, no new data is written in the RAM array on each
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
To prevent data overflow in the FWFT mode, Input Ready (IRA,IRB) will
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
Data can be read on the outputs on the LOW-to-HIGH transition of the
The Write and Read Clocks can be asynchronous or coincident.
When Read Enable (RENA/RENB) is LOW, data is loaded from the RAM
When the REN input is HIGH, the output register holds the previous data
RSF
. The Programmable
RSF
. The Full
9
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
order to access all other words, a read must be executed using REN. The
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (ORA/ORB) will go HIGH with a true read (RCLK with
REN = LOW), inhibiting further read operations. REN is ignored when the
FIFO is empty.
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EFA/EFB) will go
LOW, inhibiting further read operations. REN is ignored when the FIFO is
empty. Once a write is performed, EF will go HIGH allowing a read to occur.
The EF flag is updated on the rising edge of RCLK.
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ t
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
LD
0
0
1
1
read is performed on the LOW-to-HIGH transition of RCLK.
17
17
In the IDT Standard mode, every word accessed at Qn, including the first
In the FWFT mode, the first word written to an empty FIFO automatically
SKEW
Figure 3. Offset Register Location and Default Values
after the first write. REN does not need to be asserted LOW. In
WEN
0
1
0
1
11
11
Figure 2. Writing to Offset Registers
001FH (IDT72V805) 003FH (IDT72V815):
001FH (IDT72V805) 003FH (IDT72V815):
WCLK
007FH (IDT72V825/72V835/72V845)
007FH (IDT72V825/72V835/72V845)
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Selection
FEBRUARY 11, 2009
4295 drw 04
0
0