IDT72V825L15PF IDT, Integrated Device Technology Inc, IDT72V825L15PF Datasheet - Page 7

• Manufacturer Part Number: IDT72V825L15PF
• Description: IC SYNCFIFO 1024X18X2 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V825L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V825L15PF

normal read/write operation. When the LD pin and WEN are again set LOW,
the next offset register in sequence is written.
Q0-Q11 when the LD pin is set LOW and REN is set LOW. Data can then
be read on the next LOW-to-HIGH transition of RCLK. The first transition
of RCLK will present the Empty Offset value to the data output lines. The
next transition of RCLK will present the Full Offset value. Offset register
content can be read out in the IDT Standard mode only. It cannot be read
in the FWFT mode.
SYNCHRONOUS VS ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
during the "Configuration at Reset" cycle described in Table 3 with either
asynchronous or synchronous timing for PAE and PAF flags.
PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is
asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n=31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m=31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
TABLE 2 — STATUS FLAGS FOR FWFT MODE
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n = 31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m = 31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
129 to (256-(m+1))
130 to (257-(m+1))
The contents of the offset registers can be read on the data output lines
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
If asynchronous PAE/PAF configuration is selected (as per Table 3), the
(256-m) to 255
(n + 1) to 128
(n + 2) to 129
(257-m) to 256
1 to (n + 1)
IDT72V805
IDT72V805
1 to n
256
257
0
0
(1)
(1)
(2)
(2)
257 to (512-(m+1))
258 to (513-(m+1))
(512-m) to 511
(n + 1) to 256
(513-m) to 512
(n + 2) to 257
1 to (n + 1)
IDT72V815
IDT72V815
1 to n
512
513
0
0
(1)
(1)
(2)
(2)
Number of Words in FIFO
513 to (1,024-(m+1))
514 to (1,025-(m+1))
(1,024-m) to 1,023
(1,025-m) to 1,024
Number of Words in FIFO
(n + 1) to 512
(n + 2) to 513
1 to (n + 1)
IDT72V825
IDT72V825
1 to n
1,024
1,025
0
0
(1)
(1)
(2)
(2)
1,025 to (2,048-(m+1))
1,026 to (2,049-(m+1))
(2,048-m) to 2,047
7
(2,049-m) to 2,048
(n + 1) to 1,024
(n + 2) to 1,025
grams, see Figure 13 for asynchronous PAE timing and Figure 14 for
asynchronous PAF timing.
and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. For
detail timing diagrams, see Figure 22 for synchronous PAE timing and
Figure 23 for synchronous PAF timing.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
during the "Configuration at Reset" cycle described in Table 4 with single,
double or triple register-buffered flag output signals. The various combina-
tions available are described in Table 4 and Table 5. In general, going from
single to double or triple buffered flag outputs removes the possibility of
metastable flag indications on boundary states (i.e, empty or full condi-
tions). The trade-off is the addition of clock cycle delays for the respective
flag to be asserted. Not all combinations of register-buffered flag outputs
are supported. Register-buffered outputs apply to the Empty Flag and Full
Flag only. Partial flags are not effected. Table 4 and Table 5 summarize
the options available.
IDT72V835
1 to (n + 1)
IDT72V835
1 to n
If synchronous PAE/PAF configuration is selected , the PAE is asserted
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
2,048
2,049
0
0
(1)
(1)
(2)
(2)
2,049 to (4,096-(m+1))
2,050 to (4,097-(m+1))
(4,096-m) to 4,095
(4,097-m) to 4,096
(n + 1) to 2,048
(n + 2) to 2,049
1 to (n + 1)
IDT72V845
IDT72V845
1 to n
4,096
4,097
0
0
COMMERCIAL AND INDUSTRIAL
(1)
(1)
(2)
(2)
TEMPERATURE RANGES
FF PAF
IR PAF HF PAE OR
H
H
H
H
H
H
L
L
L
L
L
L
FEBRUARY 11, 2009
H
H
H
H
L
L
H
H
H
H
L
L
HF
H
H
H
H
H
H
L
L
L
L
L
L
PAE EF
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L