AN2638 Freescale Semiconductor / Motorola, AN2638 Datasheet - Page 9

• Manufacturer Part Number: AN2638
• Description: Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
• Manufacturer: Freescale Semiconductor / Motorola

6 Clock Jitter Effects on AC Timing
On systems where PLL experiences excessive jitter beyond the allowed AC requirement of the system, the
timing specification 30 (sp30) hold time will be in violation. As stated in the hardware specifications
document, sp30 is the minimum hold time for output signals. It is 0.5ns and is referenced to the internal
clock signal. Some of the symptoms that can occur when sp30 does not meet the specifications are
corruption on the address and data buses. In the following sections we will discuss sp30 measurement of an
ideal case with minimum jitter and a worse case scenario of clock jitter.
6.1 Ideal Case (Minimum Jitter)
Figure 12 shows a scope capture that illustrates sp30 measurement that meets the specification of 0.5 ns.
Probe 1 was connected to SDRAM CLOCK_IN and probe 2 was connected to the CAS signal on the
MPC8260. This measurement is taken in “infinite persistence” mode to capture the clock jitter.
MOTOROLA
.
3. Ensure probe ground pins are close to the signal pins
4. In terms of the scope setting, we used infinite persistence option to capture minimum/maximum of
5. The measurement should be taken while the Device Under Test (DUT) is running the application
6. The signal measurements should be taken at the mid level crossing point between SDRAM
the clock variation (jitter).
software at peak rate.
CLOCK_IN and CAS signal.
Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
Figure 12. sp30 Timing and Clock Jitter Specification
Freescale Semiconductor, Inc.
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Clock Jitter Effects on AC Timing
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