AN2638 Freescale Semiconductor / Motorola, AN2638 Datasheet - Page 3

• Manufacturer Part Number: AN2638
• Description: Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
• Manufacturer: Freescale Semiconductor / Motorola

1.3 Period Jitter
Frequency (period) jitter is the frequency deviation of the waveform from the average frequency. Period
jitter is a critical measurement for system timing margins. It is important to take period jitter measurements
into account when designing a high-speed system. Figure 3 shows an example of period jitter.
2 Possible Cause of PLL Jitter
External noise induced by a printed circuit board (PCB) can contribute to PLL noise. The effect of external
(board level) noise on PLL performance can be minimized by careful PCB layout, adequate filtering of the
PLL supplies, and insuring a clean input clock.
The power distribution on the PCB should guarantee voltage supply within the specification during
operation. The PCB layout should be such to minimize the noise coupling between the main supply and the
PLL supply. The noise level on the PLL supply (VCCSYN) affects the noise level of the PLL VCO.
Clock jitter can cause a number of undesired effects on the system, such as data corruption in the system
memory (SDRAM) due to AC timing violation.
Figure 4 shows the comparison of “SDRAM Clock” and “Internal Clock” on a typical data output signal.
The data is valid on the rising edge of the clock signal. However, because of clock jitter the rising edge of
the clock has occurred prior to the data becoming valid. In this case data corruption can occur.
MOTOROLA
f
Clk_2 “Internal_Clk”
Figure 4. Comparison of SDRAM Clock Signal with Internal Clock on typical Data Output cycle
Clk_1 “SDRAM_Clk”
Data output
Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
Freescale Semiconductor, Inc.
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Figure 3. Period Jitter
Clock Period
Clock Jitter
Clk_Jitter
Min.Output Delay
Possible Cause of PLL Jitter
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