AN2638 Freescale Semiconductor / Motorola, AN2638 Datasheet - Page 4

• Manufacturer Part Number: AN2638
• Description: Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
• Manufacturer: Freescale Semiconductor / Motorola

Phase Lock Loop (PLL)
Phase Lock Loop (PLL)
3 Phase Lock Loop (PLL)
A phase lock loop, shown in Figure 5, is a feedback system that operates on the excess phase of nominally
periodic signals. The range in which the Voltage Controlled Oscillator (VCO) can lock onto a new signal is
sometimes referred to as the PLL locking range. Once the PLL is locked, it is said to be tracking a signal.
In the PLL locked condition, the input and output PLL signals have equal frequencies with minimum phase
difference and the phase detector generates pulses whose widths are equal to the time difference between
the zero crossing of the input and output.
Because the PLL operates on the phase of signals, it is susceptible to phase noise or jitter. Phase noise at
either the input signal or the VCO can influence PLL operation.
The loop filter dynamic behavior is controlled by the value of LPF capacitor. When the Multiplication
Factor (MF) increases, the LPF capacitor must be larger (as explained in Table 10-1 in the MPC8260
PowerQUICC II™ Family Reference Manual) and the PLL bandwidth is decreased. Thus, assuming a
stable input clock, the use of a smaller MF and a higher reference clock frequency to maintain a design’s
PLL frequency minimizes the PLL jitter.
Therefore, the following items may reduce jitter:
3.1 PLL Transfer Function
In theory the PLL loop filter equivalent circuit can be shown as Figure 4 in which the internal filter capacitor
C
4
int
Input Frequency
(Reference)
Feedback
•
•
•
•
•
•
is parallel to C
Phase noise of the VCO—The PLL loop bandwidth should be maximized to reduce VCO phase
noise and lock time. The VCO’s immunity to noise that comes through the power supply or the
ground is determined mainly by internal PLL power supply noise filtering capability. Noise at the
frequency around the PLL bandwidth is a main cause of the phase jitter. High frequency power
supply noise mainly affects period jitter and cycle-to-cycle jitter, while low frequency power supply
noise is mainly filtered by the loop filter.
Phase noise at input signal—The PLL loop bandwidth should be minimized to filter the input signal
phase noise.
A clean reference clock. It is recommended that designs provide a power supply that is clean from
noise at a PLL bandwidth of 200kHz – 2MHz (or even wider for better PLL performance).
A higher reference clock frequency
A smaller MF
Well filtered PLL power supply
Phase Detector
xfc
both capacitors are in series to internal filter R
Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4)
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5. Phase Lock Loop Block
Go to: www.freescale.com
Low-Pass
Filter
Pre-Scaler
int
.
VCO
MOTOROLA
Output