AN2638 Freescale Semiconductor / Motorola, AN2638 Datasheet

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... Freescale Semiconductor, Inc. Application Note AN2638 Rev. 0, 12/2003 Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4) Clock jitter can cause unwanted effects on high-speed system design. In general it is important for the system designer to ensure proper board (PCB) layout for power and ground planes, as well as the signal layer ...

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Freescale Semiconductor, Inc. Clock Jitter Clock Jitter 1 Clock Jitter Clock jitter is defined as when the clock’s output varies—either leads or lags—from its ideal position. Clock jitter can be classified as one of the three following categories: • Cycle ...

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Freescale Semiconductor, Inc. 1.3 Period Jitter Frequency (period) jitter is the frequency deviation of the waveform from the average frequency. Period jitter is a critical measurement for system timing margins important to take period jitter measurements into account ...

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Freescale Semiconductor, Inc. Phase Lock Loop (PLL) Phase Lock Loop (PLL) 3 Phase Lock Loop (PLL) A phase lock loop, shown in Figure feedback system that operates on the excess phase of nominally periodic signals. The range ...

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Freescale Semiconductor, Inc. Rint Vin Table 3provides a brief description for each transfer function elements. Table 3. PLL Transfer Function Elements Transfer Function n H (s) LPF The PLL low pass filter of the first order ...

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Freescale Semiconductor, Inc. Phase Lock Loop (PLL) Phase Lock Loop (PLL) Rint Vin The addition modifies the transfer function as follows: xfc 3.2 Frequency Response Figure 8 shows a frequency response compression graph of filter configuration. This ...

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Freescale Semiconductor, Inc. 3.3 XFC Filter The XFC (external filter capacitor), shown in Figure 9, is critical to the operation of the main internal PLL circuits. The value of this capacitor determines the stability of the PLL and its ability ...

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Freescale Semiconductor, Inc. How to Minimize Clock Jitter How to Minimize Clock Jitter 4 How to Minimize Clock Jitter The following are possible ways to reduce clock jitter and avoid AC timing violations. 4.1 Power Supply A main factor that ...

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Freescale Semiconductor, Inc. 3. Ensure probe ground pins are close to the signal pins 4. In terms of the scope setting, we used infinite persistence option to capture minimum/maximum of the clock variation (jitter). 5. The measurement should be taken ...

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Freescale Semiconductor, Inc. Conclusion Conclusion 6.2 Worse case (Excessive Jitter) In comparison, Figure 13 illustrates the scope capture of worse-case clock jitter. Probe 1 was connected to SDRAM CLOCK_IN and probe 2 was connected to the CAS signal on theMPC8260. ...

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Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA Effects of Clock Jitter on the MPC8260 (HiP3 and HiP4) For More Information On This Product, Go to: www.freescale.com Conclusion 11 ...

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... The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2638 For More Information On This Product, Go to: www.freescale.com ...