AN2408 Freescale Semiconductor / Motorola, AN2408 Datasheet - Page 5

• Manufacturer Part Number: AN2408
• Description: Examples of HCS12 External Bus Design A Companion Note to AN2287/D
• Manufacturer: Freescale Semiconductor / Motorola

Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated
The following schematic demonstrates the interface of two 8-bit SRAMs to provide word access to the
external memory interface. It uses expanded wide mode in order to support word (x16) access to the
external device.
Comments:
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
The following figures are logic analyzer traces showing the wide mode access available. The
generated by a word access to the external memory space configured in wide mode.
byte access, and
that control the byte accesses.
Freescale Semiconductor
PE3
PE4
PE2
•
•
•
MCU ADDR[0]
MCU ADDR[1]
MCU ADDR[2]
MCU ADDR[3]
MCU ADDR[4]
MCU ADDR[5]
MCU ADDR[6]
MCU ADDR[7]
MCU ADDR[8]
MCU ADDR[9]
MCU ADDR[10]
MCU ADDR[11]
MCU ADDR[12]
MCU ADDR[13]
MCU ADDR[14]
MCU ADDR[15]
MCU LSTRB
MCU ECLK
MCU R/W
The least significant address line is used to implement byte access to the word wide memories.
The MCU’s LSTRB signal and the ADDR[0] signals are used to select high and low byte access to
the external devices. If this is not required (as in the case of read only memory), these signals are
not needed.
The ‘374 type latch and the SRAM access speed will require at least one additional MCU clock
stretch to access these devices or reduced MCU speed.
Memory is available from $4000–$7FFF.
Figure 6
Figure 3. Word-Wide SRAM Interface (Wide Mode) ECLK Gated
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
48
25
24
1
is an odd byte access. Notice the behavior of the ADDR0 and LSTRB signals
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1CLK
2CLK
1OE
2OE
4
5
U6
74FCT374/SO
74FCT16374/SO
Examples of HCS12 External Bus Design, Rev. 2
U9B
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
6
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
10
1
2
9
74FCT374/SO
74FCT374/SO
Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated
U9A
U9C
3
8
2
3
1
U8A
74FCT139A/SO
A
B
G
Y0
Y1
Y2
Y3
4
5
6
7
WE*
OE*
14
13
15
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
U8B
74FCT139A/SO
A
B
G
Y0
Y1
Y2
Y3
$4000
12
11
10
9
10
25
24
21
23
22
27
20
26
10
25
24
21
23
22
27
20
26
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
U5
U7
Figure 5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
OE
WE
CS1
CS2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
OE
WE
CS1
CS2
6264/SO
6264/SO
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
11
12
13
15
16
17
18
19
Figure 4
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
is an even
was
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
5