AN2408 Freescale Semiconductor / Motorola, AN2408 Datasheet
AN2408
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AN2408 Summary of contents
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... This application note primarily uses random access memory (RAM) in the design examples because of its speed and well-known architecture. It also provides information necessary to implement other architectures. This product incorporates SuperFlash © Freescale Semiconductor, Inc., 2004. All rights reserved. ® technology licensed from SST. AN2408/D Rev. 2, 8/2004 ...
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Example #1 — Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated Precepts These precepts apply to all the following examples: • In some of the designs, there is no data buffer. These designs assume that the VOH levels of the external ...
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MCU ADDR[0] PB0 MCU ADDR[1] PB1 MCU ADDR[2] PB2 MCU ADDR[3] PB3 MCU ADDR[4] PB4 MCU ADDR[5] PB5 MCU ADDR[6] PB6 MCU ADDR[7] PB7 MCU ADDR[8] PA0 MCU ADDR[9] PA1 MCU ADDR[10] PA2 MCU ADDR[11] PA3 MCU ADDR[12] PA4 MCU ...
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Example #1 — Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated Figure 2. Byte-Wide SRAM Interface (Word Write $AAAA) as Two Access Cycles 4 Examples of HCS12 External Bus Design, Rev. 2 Freescale Semiconductor ...
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Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated The following schematic demonstrates the interface of two 8-bit SRAMs to provide word access to the external memory interface. It uses expanded wide mode in order to support word (x16) ...
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Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated Figure 4. Expanded Wide Word Access ($1234) 6 Examples of HCS12 External Bus Design, Rev. 2 Freescale Semiconductor ...
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Figure 5. Expanded Wide Even Byte Access ($AA) Freescale Semiconductor Example #2 — Word-Wide SRAM Interface (Wide Mode) ECLK Gated Examples of HCS12 External Bus Design, Rev ...
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Example #3 — Byte-Wide SRAM Interface with Paging Figure 6. Expanded Wide Odd Byte Access ($55) Example #3 — Byte-Wide SRAM Interface with Paging In the following schematic, a 128K SRAM device is attached to the external bus in expanded ...
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ADDR/DATA0 PB0 ADDR/DATA1 ADDR/DATA8 PB1 ADDR/DATA2 ADDR/DATA9 PB2 ADDR/DATA3 ADDR/DATA10 PB3 ADDR/DATA4 ADDR/DATA11 PB4 ADDR/DATA5 ADDR/DATA12 PB5 ADDR/DATA6 ADDR/DATA13 PB6 ADDR/DATA7 XADDR14 PB7 XADDR15 ADDR/DATA8 XADDR16 PA0 ADDR/DATA9 XADDR19 PA1 ADDR/DATA10 PA2 ADDR/DATA11 PA3 ADDR/DATA12 PA4 ADDR/DATA13 PA5 GND ADDR/DATA14 ...
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Example #4 — Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated Example #4 — Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated The following schematic demonstrates the interface to a 8-bit SRAM to provide word access to the external memory interface. It ...
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MCU_XADDR[14] 3 PTK0 MCU_XADDR[15] 4 PTK1 MCU_XADDR[16] 7 PTK2 MCU_XADDR[17] 8 PTK3 MCU_XADDR[18] 13 PTK4 MCU_XADDR[19] 14 PTK5 MCU ADDR[0] 47 PB0 MCU ADDR[1] 46 PB1 MCU ADDR[2] 44 PB2 MCU ADDR[3] 43 PB3 MCU ADDR[4] ...
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Example #4 — Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated Figure logic analyzer trace showing the narrow mode access with ECS gating. This word access is divided into two 8-bit accesses by the MCU. Notice that the ...
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EXTERNAL READ CYCLE S0 S1 SYSCLK ECLK ECLK t CSD ECS/XCS t AD ADDR ADDR/DATA t RWD R/W RAM_R/W t :373 P LATCHED_ADDR RAM_DATA Freescale Semiconductor Example #4 — Byte-Wide SRAM Interface (Narrow Mode) XCS/ECS Gated ...
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Example #5 — Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated Example #5 — Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated The following schematic demonstrates the interface to a 16-bit SRAM to provide word access to the external memory interface. It ...
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Figure logic analyzer trace showing expanded wide mode access with ECS gating. Notice that even though the clock stretching is enabled, significant reduction in access time is available, depending on SRAM access speed. Figure 14. Expanded Wide ...
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Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated Example #6 — Word-Wide FLASH Interface with Banking – XCS/ECS Gated The following schematic demonstrates the interface to a 16-bit FLASH memory device to provide word wide access. It ...
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Memory Map External FLASH Example #7 — Word-Wide External Device Interface – 100BASE-T Ethernet Figure 18 demonstrates the interface to a 16-bit ...
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Example #7 — Word-Wide External Device Interface – 100BASE-T Ethernet These buffers will create desired delay for address bus GND U29 24 2OE 1 1OE 25 VCC_5V 2LE 48 1LE PAD15 26 23 2D8 2Q8 PAD14 27 22 PAD[0..15] 2D7 ...
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Expansion Bus settings */ /**************************************************************************/ Regs.pear.byte = 0x0C; // %00001100 // // // // // // // // // The PEAR register is known as the port E assignment register used to control the setting of the ...
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Example #8 — Software External Interface Regs.misc.byte = 0x07; // %00000111 // // // // // // // // // The MISC register is used to control some of the miscellaneous functions needed for bus control. The EXSTR1 and EXSTR0 ...
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DE00 1017 [04] 4C0810 101A [01] B754 101C [02] 1B83 101E [06] 0A Freescale Semiconductor 5;** Flash software ...
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Conclusion ADDR[1] PTH0 ADDR[2] PTH1 ADDR[3] PTH2 ADDR[4] PTH3 ADDR[5] PTH4 ADDR[6] PTH5 ADDR[7] PTH6 ADDR[8] PTH7 ADDR[9] PTP0 ADDR[10] PTP1 ADDR[11] PTP2 ADDR[12] PTP3 ADDR[13] PTP4 ADDR[14] PTP5 ADDR[15] PTP6 ADDR[16] PTP7 ADDR[17] PTJ0 ADDR[18] PTJ1 OE* PE3 MCU ...
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Freescale Semiconductor Examples of HCS12 External Bus Design, Rev. 2 This page is intentionally blank. 23 ...
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... Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com AN2408/D Rev. 2, 8/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...