AN2408 Freescale Semiconductor / Motorola, AN2408 Datasheet - Page 14

• Manufacturer Part Number: AN2408
• Description: Examples of HCS12 External Bus Design A Companion Note to AN2287/D
• Manufacturer: Freescale Semiconductor / Motorola

Example #5 — Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated
Example #5 — Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated
The following schematic demonstrates the interface to a 16-bit SRAM to provide word access to the
external memory interface. It uses expanded wide mode in order to support word (x16) access to the
external device. It has the addition of logic to support additional banks of external memory.
Comments:
14
PTK6/7
PTK0
PTK1
PTK2
PTK3
PTK4
PTK5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PE3
PE4
PE2
•
•
•
•
The XCS or ECS signal is required because the external device does not possess the active-high
chip-enable needed for using the ECLK signal to activate the external device. If the ECS signal is
implemented, the ROMON bit must be clear, as internal memory has precedence over external
memory. Because not all HCS12 Family members have the XCS signal, this design will not be
applicable in all instances. The system designer should assess the overall design to determine
applicability.
This design introduces memory paging. An additional latch is provided to acquire the extended
address lines XAD[19..14]. This latch is not required in all instances. The system designer should
carefully study the device specifications and relevant errata to verify the system design.
The ECS/XCS signals improve access time. Replacing the ‘374 type latches with a ‘373
transparent device allows the address to be presented to the memory device in advance of the
rising ECLK edge. This enhancement and careful memory selection will allow higher speed access
to the external device.
U22 — (FCT139) may be replaced with NAND gate decoding, if an extra NAND is required for
system design. See
MCU ADDR[0]
MCU ADDR[1]
MCU ADDR[2]
MCU ADDR[3]
MCU ADDR[4]
MCU ADDR[5]
MCU ADDR[6]
MCU ADDR[7]
MCU ADDR[8]
MCU ADDR[9]
MCU ADDR[10]
MCU ADDR[11]
MCU ADDR[12]
MCU ADDR[13]
MCU ADDR[14]
MCU ADDR[15]
MCU_XADDR[14]
MCU_XADDR[15]
MCU_XADDR[16]
MCU_XADDR[17]
MCU_XADDR[18]
MCU_XADDR[19]
MCU ECS/XCS
MCU LSTRB
MCU ECLK
MCU R/W
Figure 13. Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated
13
14
17
18
11
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
48
25
24
3
4
7
8
1
1
U18
74FCT373/SO
U19
74FCT16373/SO
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1LE
2LE
1OE
2OE
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
Figure 3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Examples of HCS12 External Bus Design, Rev. 2
XADDR[14]
XADDR[15]
XADDR[16]
XADDR[17]
XADDR[18]
XADDR[19]
ADDR[0]
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[8]
ADDR[9]
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
U9 — (FCT00) for implementation.
2
3
1
2
3
1
U21A
74FCT139A/SO
U22A
74FCT139A/SO
A
B
G
A
B
G
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
4
5
6
7
4
5
6
7
14
13
15
U21B
74FCT139A/SO
WE*
OE*
A
B
G
Y0
Y1
Y2
Y3
12
11
10
9
$8000
$8000
18
19
20
21
22
23
24
25
26
27
42
43
44
39
41
40
17
1
2
3
4
5
6
U20
AS7C4098/SO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
LB
OE
UB
WE
CE
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
Freescale Semiconductor
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
DATA[13]
DATA[14]
DATA[15]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7