CY28349B Cypress Semiconductor, CY28349B Datasheet - Page 14

• Manufacturer Part Number: CY28349B
• Description: FTG
• Manufacturer: Cypress Semiconductor

Table 5. Register Summary (continued)
Program the CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N+3)/(M+3).
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
Document #: 38-07454 Rev. *A
CPU_FSEL_N,
CPU_FSEL_M
ROCV_FREQ_SEL
ROCV_FREQ_N[7:0],
ROCV_FREQ_M[6:0]
WD_EN
WD_TO_STATUS
WD_TIMER[4:0]
WD_PRE_SCALER
RST_EN_WD
RST_EN_FC
Name
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same SMBus bus operation.
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits
in SMBus control bytes.
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0].
When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a
Watchdog Timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is
cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used.
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block Write to update both
registers within the same SMBus bus operation.
0 = Stop and reload Watchdog Timer
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE).
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the
pre-scaler.
The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 4.
The ratio of (N+3) and (M+3) need to be greater than “1”
[(N+3)/(M+3) > 1].
The following table lists set of N and M values for different
frequency output ranges.This example use a fixed value for
the M-Value Register and select the CPU output frequency by
changing the value of the N-Value Register.
Description
CY28349B
Page 14 of 22