CY28349B Cypress Semiconductor, CY28349B Datasheet
CY28349B
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CY28349B Summary of contents
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... GND_PCI VDD_PCI PCI_F0:2 PCI0:6 VDD_48MHz 3V66_3/48MHz_1 VDD_PCI VTT_PWRGD# VDD_48MHz 48MHz_0 RST# GND_48MHz *FS0/48MHz_0 24_48MHz *FS1/24_48MHz 2 VDD_48MHz RST# • 3901 North First Street • CY28349B ® 4 CPU and Chipsets 3V66 PCI REF 48M [ REF0/MULTSEL0 GND_REF ...
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... For Intel Brookdale – G platforms, this output will be used as the reference clock for both USB host controller and SIO devices. We recommend system designer to configure this output as 48 MHz and “HIGH Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively. CY28349B Pin Description Page ...
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... PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. G Ground Connection: Connect all ground pins to the common system ground plane. P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. G Analog Ground Connection: Ground for core logic, PLL circuitry. CY28349B Pin Description Page ...
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... IREF = 5. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2. 475 1%, IREF = 2.32 mA CY28349B Output Current 4*Iref 1. 4*Iref 1. 5*Iref 1.25V @ 5*Iref 1. 6*Iref 1. ...
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... Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge ... Data bytes from slave/Acknowledge ... Data byte N from slave – 8 bits ... Not Acknowledge ... Stop Byte Read Protocol Bit Description 1 Start 2:8 Slave address – 7 bits CY28349B Page ...
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... Reserved ‘011’ = Reserved ‘100’ = ± 0.25% ‘101’ = – 0.5% ‘110’ = ±0.5% ‘111’ = ±0.38% SW Frequency selection bits. See Table 4. Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28349B Description Power On Default Power On Default 1 1 ...
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... HW control; IREF multiplier is determined by MULTSEL[0:1] input pins control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh IREF 01 = Ioh IREF 10 = Ioh IREF 11 = Ioh IREF Reserved Reserved Reserved Reserved Reserved CY28349B Power On Default Power On Default 1 ...
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... If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and generate Reset if RST_EN_WD is enabled. CY28349B Power On Default X X ...
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... Stop and reload Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: CY28349B will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog Timer time-out occurs. Under recovery frequency mode, CY28349B will not respond to any attempt to change output frequency via the SMBus control bytes ...
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... Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL From latched FS[4: From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] CY28349B Power On Default ...
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... When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved. Write with “1” Reserved. Write with “1” CY28349B Power On Default Power On Default ...
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... CY28349B Pin Description Pin Description PLL Gear Constants 3V66 PCI 67.1 33.6 48.00741 67.3 33.6 48.00741 72.0 36.0 48.00741 67.5 33.7 48.00741 76.0 38.0 48.00741 78.0 39.0 48.00741 80.0 40.0 48.00741 82.0 41.0 48.00741 63.0 31.5 48.00741 65 ...
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... Watchdog Timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized in Table 5. Description CY28349B PLL Gear Constants 3V66 PCI (G) 68 ...
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... The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. The following table lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. CY28349B Page ...
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... Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges Gear Constants 50 MHz–129 MHz 48.00741 130 MHz–248 MHz 48.00741 Document #: 38-07454 Rev. *A Fixed Value for Range of N-Value Register M-Value Register for Different CPU Frequency 93 45 CY28349B 97–255 127–245 Page ...
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... DD 0 < V < For I =6*IRef Configuration OH REF, 48 MHz 3V66, PCI REF, 48MHz 3V66, PCI, Three-state /V = 3.465V 133 MHz DD_CORE DD33 CPU 3.465V DD_CORE DDQ3 CY28349B [2] Min. Max. 3.135 3.465 22 14.318 14.318 Min. Max. Unit /2 2 – – ...
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... CPU and PCI clock stabilization from power-up Measured with test loads Measured with test loads Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 3.3V. When V = 2.5V, duty cycle is measured at 1.25V. DD CY28349B Min. Max 175 700 oh 0.5 2.0 1.0 4 ...
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... Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 Document #: 38-07454 Rev CY28349B Page ...
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... CLK Ordering Information Pkg. Ordering Code Name CY28349BOC O48 CY28349BOCT O48 Document #: 38-07454 Rev Package Type 48-pin SSOP 48-pin SSOP – Tape and Reel CY28349B t 8B Operating Range Commercial, 0°C to 70°C Commercial, 0°C to 70°C Page ...
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... 100 MHz 0.005 =VIA to respective supply plane layer CY28349B ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-lead Shrunk Small Outline Package O48 CY28349B 51-85061-*C Page ...
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... Document Title: CY28349B FTG for Intel Document Number: 38-07454 Issue REV. ECN NO. Date ** 117127 08/13/02 *A 122932 12/17/02 Document #: 38-07454 Rev. *A ® ® Pentium 4 CPU and Chipsets Orig. of Change RGL New Data Sheet RBI Add power up requirements to operating condition information. CY28349B Description of Change Page ...