CY28349B Cypress Semiconductor, CY28349B Datasheet - Page 13

• Manufacturer Part Number: CY28349B
• Description: FTG
• Manufacturer: Cypress Semiconductor

Table 4. Frequency Selection Table (continued)
Programmable Output Frequency, Watchdog
Timer and Recovery Output Frequency
Functional Description
The Programmable Output Frequency feature allows users to
generate any CPU output frequency from the range of 50 MHz
to 248 MHz. Cypress offers the most dynamic and the simplest
programming interface for system developers to utilize this
feature in their platforms.
Table 5. Register Summary
Document #: 38-07454 Rev. *A
Pro_Freq_EN
FS_Override
SEL4
FS4
1
1
1
1
1
1
1
1
1
1
1
1
1
Name
SEL3
FS3
0
0
0
0
0
1
1
1
1
1
1
1
1
Input Conditions
SEL2
FS2
Programmable output frequencies enabled
0 = Disabled (default)
1 = Enabled.
When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.
When it is enabled, the CPU output frequency will be determined by the programmed value of
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between
CPU and other frequency outputs.
When Pro_Freq_EN is cleared or disabled,
0 = Select operating frequency by FS input pins (default)
1 = Select operating frequency by SEL bits in SMBus control bytes.
When Pro_Freq_EN is set or enabled,
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default)
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes.
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
FS1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
170.0
175.0
180.0
185.0
190.0
166.8
100.2
133.6
200.4
166.6
100.0
200.0
133.3
CPU
The Watchdog Timer and Recovery Output Frequency
features allow users to implement a recovery mechanism
when the system hangs or gets unstable. System BIOS or
other control software can enable the Watchdog Timer before
they attempt to make a frequency change. If the system hangs
and a Watchdog Timer time-out occurs, a system reset will be
generated and a recovery frequency will be activated.
All of the related registers are summarized in Table 5.
Description
Output Frequency
3V66
68.0
70.0
72.0
74.0
76.0
66.7
66.8
66.8
66.8
66.6
66.6
66.6
66.6
34.0
35.0
36.0
37.0
38.0
33.4
33.4
33.4
33.4
33.3
33.3
33.3
33.3
PCI
CY28349B
Constants
PLL Gear
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
Page 13 of 22
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