AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 18

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

SDRAM Power Control Features
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The DRAM controller can initiate two kinds of power control features:
SDRAM self-refresh mode is controlled by the RE bit in the DRAMC register. By setting the RE bit to ’1’,
the DRAM controller will issue a self-refresh mode command.
The SDRAM draws the minimal amount of power when in self-refresh mode. The DRAM controller can
also be disabled after the SDRAM enters self-refresh mode.
Power-down modes allows the SDRAM to be supended when not in use. It differs from self-refresh mode
in that it does not require a wakeup period when access occurs. See section 3.2.4 of this document for
details on power down modes.
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Self-refresh mode.
Power-down mode.
SDRAM Power Control Features
Design Considerations for Interfacing SDRAM with MC68VZ328
Figure 12. Self-refresh Event
Pre-Publication Draft
Refer to Table 1 for signal description