AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 10

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

SDRAM Control Registers
The EN bit of the CSD register should be set to one to enable this chip-select. Also, the WS3-1 bits can be
used to introduce a number of wait states if required.
3.1.3
The DragonBall VZ chip-select module incorporates an Early Cycle Detect (ECD) feature for dynamic
memory. In a normal CS (without ECD) scenario, the CS signal is preceeded by an internal Address Strob
(ASB) signal from the 68K core. The ECD feature works off the fact that the ASB is itself preceeded by an
"early" ASB signal from the 68K core. By using the "early" ASB signal to derive the CS signal, both read
and write cycles to SDRAM can be shortened by one clock cycle.
10
0xFFFFFFFF
0x02000000
0x02FFFFFF
0x01FFFFFF
0x00000000
0x01000000
Chip-Select Control Register 2 (CSCTRL2)
For 32MB SDRAM, the chip-select size is first set to 16 MB, and then the
COMB bit (bit10) of the CSD register is set to ’1’. The COMB bit
effectively combines the memory space of CSD1 to that of CSD0 allowing
CSD0 to address a full 32MB.
Design Considerations for Interfacing SDRAM with MC68VZ328
1) This bit resides in the CSCTRL1 register.
2) Use this setting for 32MB SDRAM as well.
CSD0
Figure 3. Combining CSD0 and CSD1 for 32MB SDRAM
CSD1
DSIZ3
1
1
1
NOTE: 32 MB SDRAM Chip-Select Size
Table 5. SDRAM Chip-Select Size
0
0
16MB
16MB
Pre-Publication Draft
SIZ [3:1]
0
0
CSD Register:
COMB bit = 1
0
1
0xFFFFFFFF
0x02FFFFFF
0x00000000
0x01000000
SDRAM Size
16MB
8MB
2
CSD0
32MB