AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 15

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

All the steps above has to be done in that order followed by a number of no-ops to allow the SDRAM to
initialize properly.
See the next section for example code on SDRAM initialization.
3.2.4
The SDPWDN register controls how the SDRAM enters power-down mode. The power-down mode can
reduce SDRAM power consumption by negating the SDCE signal when SDRAM is not being accessed.
During power-down mode, refresh cycles continue to be issued to the SDRAM by the DRAM controller.
3.2.4.1
When the APEN bit is set, the SDCE will be negated after every access to the SDRAM.
3.2.4.2
When the PDEN bit is set, the SDCE signal will negate when the SDRAM has been precharged and the
PDTOUT time-out condition has been meet.
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•
Start SDRAM refresh cycles using the RE bit in the SDCTRL register
Set mode register of the SDRAM with the MR bit
SDRAM Power-down Register (SDPWDN)
Active Power-down Mode
Precharge Power-down Mode
IP = 0, RE = 1, MR = 0
IP = 0, RE = 1, MR = 1
The MR bit passes the CAS latency setting to the mode register of the
SDRAM. The load mode register command programs the SDRAM to Cas
latency 1 or 2 depending on the CL bit. The CL bit should be set to the
proper latency period prior to setting the MR bit.
Figure 9. Active Power-down Mode
SDRAM Control Registers
Pre-Publication Draft
Refer to Table 1 for signal description
DRAM Controller Registers
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