AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 11

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

Using the PK3/UDS signal as a reference in Figure 4 and Figure 5, setting the ECDD bit can improve
SDRAM operation during CPU access to the SDRAM by asserting SDCSx early. LCDC DMA access is
not affected by the ECD feature since the CPU is not involved during the access.
For more information on ECD settings, see section 6.3.6 in the VZ User Manual
3.2
The DragonBall VZ DRAM Controller is designed to support SDRAM up to 32MB. Four registers handle
the configuration and operation of SDRAM.
DRAM Controller Registers
Early ASB
Sample
PreC. Act
PreC. Act
Figure 5. SDRAM Read/Write with ECD
Sample
ASB
Figure 4. Normal SDRAM Read/Write
SDRAM Control Registers
Read
Read
Pre-Publication Draft
Early ASB
Sample
Sample
ASB
PreC. Act
PreC. Act
Refer to Table 1 for signal description
Refer to Table 1 for signal description
Write
Write
DRAM Controller Registers
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