DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 99

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Table 16-2: Error Insertion examples
Value
000h
001h
002h
3FFh
NOEL1A: NUMBER of ERRORS LEFT 1 FRAMER A (Address = 83 Hex)
NOEL1B: NUMBER of ERRORS LEFT 1 FRAMER B (Address = 88 Hex)
NOEL2A: NUMBER of ERRORS LEFT 2 FRAMER A (Address = 84 Hex)
NOEL2B: NUMBER of ERRORS LEFT 2 FRAMER B (Address = 89 Hex)
Number Of Errors Left Registers. The Host can read the NOEL registers at any time (to determine
how many errors are left to be inserted) by toggling the RNOE bit in the Error Rate Control registers
(ERCA and ERCB) from a 0 to a 1. After the RNOE bit is toggled, the Host may read the NOEL
registers after waiting at least 972 ns (1.5 clock periods).
17.
The DS2196 has an enhanced HDLC controller configurable for use with the Facilities Data Link or
DS0s. There are 64 byte buffers in both the transmit and receive paths. The user can select any DS0 or
multiple DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. See
Figure 21-7 for details on formatting the transmit side. Note that TBOC.6 = 1 and TDC1.7 = 1 cannot
exist without corrupting the data in the FDL. For use with the FDL, see section 18. See Table 17-1 for
configuring the transmit HDLC controller.
Table 17-1: TRANSMIT HDLC CONFIGURATION
DS0(s)
FDL
Disable
(MSB)
C7
SYMBOL
–
Function
HDLC CONTROLLER
C9
C0
do not create any
errors
create a single error
create 2 errors
create 1023 errors
C6
Write
–
POSITION
NOEL2.1
NOEL1.0
C5
–
TBOC.6
no errors left to be
inserted
1 error left to be inserted
2
inserted
1023 errors left to be
inserted
0
1
0
errors
C4
–
NAME AND DESCRIPTION
MSB of the 10–bit Number of Errors Left Counter
LSB of the 10–bit Number of Errors Left Counter
Read
left
to
TDC1.7
C3
–
99 of 157
1
0
0
be
C2
–
TCR1.2
1 or 0
1 or 0
C1
C9
1
(LSB)
C0
C8
NOEL1
NOEL2
DS2196