DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 6

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

1. INTRODUCTION
The DS2196 is a derivative of the DS21352 T1 SCT. The feature set has been optimized for transport
applications commonly found in T1 transmission equipment. The DS2196 register map and register bit
definitions are compatible with the DS21352/DS21552, allowing for easy migration to the DS2196.
Interface designs requiring per-channel code insertion, elastic stores, and ANSI 1’s density monitoring
should use the DS21352 or DS21552.
1.1 Feature Highlights
§ Main features
§ 8-bit parallel control port
§ HDLC Support
§ ANSI T1.403-1998 support
§ Format Conversion
§ LIU
§ DS1 Idle Code Generation
§ In-band repeating pattern generator and
– Two full-featured independent framers
– Short/long haul LIU
– 100-pin LQFP small package
– 3.3V operation with 5V tolerant I/O
– Multiplexed or nonmultiplexed buses
– Intel or Motorola formats
– Polled or interrupt environments
– Two independent HDLC controllers
– 64-byte Rx and Tx buffers
– Access FDL or single/multiple DS0
channels
– NPRMs
– SPRMs
– RAI-CI detection and generation
– AIS-CI detection and generation
– D4 to ESF framing
– ESF to D4 framing
– Long and short-haul support
– Receive sensitivity: 0dB to -36dB
– 32-bit or 128-bit crystal-less jitter
– DSX-1 and CSU line buildout options
– Provisions for custom waveform
– User-defined
– Fixed 7F Hex
– Digital milliwatt
detector
– Programmable pattern generator
– Three programmable pattern detectors
attenuator
generation
6 of 157
§ Programmable on-chip bit error-rate testing
§ Payload Error Insertion
§ Function Isolation
§ Supports both NRZ and bipolar interfaces
§ F-bit corruption for line testing
§ Programmable output clocks for Fractional
§ Fully independent transmit and receive
§ Large path and line error counters including
§ Ability to calculate and check CRC6
§ Ability to generate Yellow Alarm according
§ Per channel loopback
§ RCL, RLOS, RRA, and RAIS alarms
§ Hardware pins to indicate receive loss-of-
§ IEEE 1149.1 JTAG Boundary Scan
– Patterns from 1 to 8 bits or 16 bits in
– Pseudorandom patterns including QRSS
– User-defined repetitive patterns
– Daly pattern
– Error insertion
– Bit and error counts
– Error insertion in the payload portion of
– Errors can be inserted over the entire
– Insertion options include continuous and
– All key signals are routed to pins
– LIU, Framer A, and Framer B can be
T1
functionality in each framer
BPV, CV, CRC6, and framing bit errors
according to the Japanese standard
to the Japanese standard
interrupt on change of state
sync and receive bipolar violations
length
the T1 frame in the transmit path
frame or selected channels
absolute number with selectable insertion
rates
disconnected from each other