DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 72

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

RDS0MA: RECEIVE DS0 MONITOR REGISTER FRAMER A
(Address = 1F Hex)
RDS0MB: RECEIVE DS0 MONITOR REGISTER FRAMER B
(Address = BF Hex)
11.
The DS2196 can replace data on a channel–by–channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive
direction is from the T1 line to the backplane and is covered in Section 11.2.
11.1 TRANSMIT SIDE CODE GENERATION
The Transmit Idle Registers (TIR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows
the same 8–bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0
control bit must be set to 0.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Bit 7 stuffing will occur over the programmed
Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
Loopback (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RSYNC to
TSYNC.
(MSB)
SYMBOL
B1
PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK
B1
B2
B3
B4
B5
B6
B7
B8
B2
POSITION
RDS0M.7
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
B3
NAME AND DESCRIPTION
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be received).
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
B4
72 of 157
B5
B6
B7
(LSB)
B8
DS2196