AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 2

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

AN1212/D
Features
2
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
The SAE Recommended Practice J1850 was developed by the Society of
Automotive Engineers as a method of medium speed (Class B) serial multiplex
communication for use in the automotive environment. Serial multiplex
communication (MUX) is a method of reducing wiring requirements while
increasing the amount and type of data which can be shared between various
components in the automobile. This is done by connecting each component, or
node, to a serial bus, consisting of either a single wire or a twisted pair. Each
node collects whatever data is useful to itself or other nodes (wheel speed,
engine RPM, oil pressure, etc.), and then transmits this data onto the MUX bus,
where any other node which needs this data can receive it. This results in a
significant improvement in data sharing, while at the same time eliminating the
need for redundant sensing systems.
The J1850 protocol encompasses the lowest two layers of the ISO open
system interconnect (OSI) model, the data link layer and the physical layer. It
is a multi-master system, utilizing the concept of carrier sense multiple access
with collision resolution (CSMA/CR), whereby any node can transmit if it has
determined the bus to be free. Non-destructive arbitration is performed on a
bit-by-bit basis whenever multiple nodes begin to transmit simultaneously.
J1850 allows for the use of a single or dual wire bus, two data rates (10.4 kbps
or 41.7 kbps), two bit encoding techniques (pulse-width modulation or variable
pulse-width modulation), and the use of CRC or Checksum for error detection,
depending upon the message format and modulation technique selected.
A J1850 message, or frame, consists of a start of frame (SOF) delimiter, a one-
or three-byte header, zero to eight data bytes, a CRC or Checksum byte, an
end of data (EOD) delimiter, and an optional in-frame response byte, followed
by an end of frame (EOF) delimiter. Frames using a single byte header are
transmitted at 10.4 kbps, using VPW modulation, and contain a Checksum byte
for error detection (see
header or a three-byte consolidated header can be transmitted at either
41.7 kbps or 10.4 kbps, using either PWM or VPW modulation techniques, and
contain a CRC byte for error detection (see
Freescale Semiconductor, Inc.
For More Information On This Product,
IDLE
BUS
Figure 2. Consolidated One-Byte Header Frame Format
IDLE
BUS
Go to: www.freescale.com
SOF HEADER
Figure 1. Single Byte Header Frame Format
SOF HEADER
Figure
DATA 1
DATA 1
1). Frames using a one-byte consolidated
DATA n CHECKSUM EOD
DATA n CRC
Figure 2
EOD
and
IFR
IFR
Figure
EOF
EOF
IDLE
BUS
IDLE
BUS
3).
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