AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 12

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

AN1212/D
Message Buffers
12
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
The in-frame response (IFR) input determines whether the JCI will transmit,
and expect to receive, an in-frame response during the IFR segment of a frame.
If the IFR input is at a logic 1, the JCI will transmit its physical node address as
a single byte IFR without CRC. The JCI will also expect to receive and IFR each
time it transmits a frame onto the MUX bus.
If arbitration is lost while the JCI is attempting to transmit an IFR during the IFR
segment of a frame, the JCI will not make another attempt to transmit an IFR
within that frame. If the JCI does not receive an IFR during the IFR segment of
a message it has transmitted, it will consider that to be a transmission error.
If the IFR input is at a logic 0, then the JCI will neither transmit an IFR nor
expect to receive an IFR when it transmits a frame onto the MUX bus.
The I.D. inputs (ID7:0) are used to input the physical address of the node.
These inputs are normally hardwired in the application to either a logic 0 or
logic 1, and are latched into the JCI on the rising edge of a reset pulse.These
inputs could be connected to an I/O port of the host MCU, but the JCI would
have to be reset by the host MCU each time it wished to change the physical
address of the node.
For more information on each of these inputs functions, refer to the J1850
Communications Interface Specification, Chapter 3: Operating Modes, and
Chapter 4: MCU Interface.
The JCI contains a single buffer for storing messages for transmission onto the
MUX bus, and two buffers for storing messages received from the MUX bus.
Each buffer can hold up to 11 bytes, allowing the JCI to transmit and receive
the maximum frame length allowed by J1850 (11 bytes + CRC byte).
The transmit (Tx) buffer is an 11-byte buffer into which the host MCU loads all
necessary header and data bytes to be transmitted onto the multiplex bus. The
CRC byte is calculated and appended onto the frame by the JCI during
transmission. The Tx buffer can hold only one complete message at a time. In
either handshake interface mode, the host MCU asserts the STX input to inform
the JCI that new message data is being transmitted and monitors the BSY
output to determine the status of the Tx buffer. In the enhanced SPI mode, the
host MCU loads the Tx buffer through a series of command bytes and monitors
the status of the Tx buffer via the status byte.
Once a complete message has been loaded into the Tx buffer, any further
attempts by the host MCU to transmit data to the JCI will be ignored until the
JCI has transmitted the current frame. Once the data has been emptied from
the buffer, the JCI will then accept data for a new message. If the host MCU
wishes to transmit a new message to the JCI before the current one has been
transmitted, it can empty the Tx buffer by asserting the FLUSH input in either
handshake interface mode or through use of the "Flush Tx FIFO" command in
the enhanced SPI mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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