AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 17

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

Setup
MOTOROLA
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
This setup routine is in two parts:
It should only be necessary to run the setup routines following a host reset, or
possibly following the detection of a communication problem on the MUX bus.
All of the setup procedures described below can be performed by calling the
subroutine JCIRST.
The host MCU RAM is initialized with six bytes reserved for data transfer
commands, a single 11-byte transmit message buffer, plus two bytes for
transmit control, and a received message buffer pointer and 8-byte received
message buffer corresponding to each functional I.D. the user’s application
must recognize. The use of each RAM location will be explained as it is utilized.
Following a reset of the MC68HC705C8, three host registers are initialized for
communication with the JCI. Two port C I/O lines (PC0:1) are configured as
outputs, with PC0 connected to the CS input of the JCI to control serial
communication and PC1 connected to the RESET input to allow the host MCU
to reset the JCI through software. The serial peripheral interface control
register (SPCR) is configured for SPI interrupt disabled, SPI enabled, master
mode, CPOL = CPHA = 1, and bit rate configured for 500 kHz SPI
communication. The OPTION register is configured for RAM0 = RAM1 = 1 (128
additional bytes of RAM), and the IRQ input is programmed for negative edge-
sensitivity.
The host MCU must then load the RAM location "txcntrl" with the value $40.
"txcntrl" is used for tracking the status of messages transmitted to the JCI and
messages transmitted by the JCI onto the MUX bus. The use of "txcntrl" will be
explained more fully in Transmitting.
The only other initialization required in the host MCU is the initialization of the
received message buffer pointers (RMBP). Each RMBP is loaded with the
starting address of each corresponding received message buffer. In this
example, there are four received message buffers. However, the number of
these buffers can be increased, with the only limit being the amount of RAM
available and the amount of time the user is willing to spend sorting received
messages.
Once the host MCU has completed initializing its internal RAM and registers,
the host must perform the necessary initialization of the JCI. This simply
involves releasing the RESET input, delaying to allow the JCI’s internal
registers to reset to a known state, and then loading the ACR and AMR
registers. The values to be loaded in the ACR and AMR registers are assigned
in the equates segment, and each is loaded by calling the subroutines
LOADACR and LOADAMR, respectively. Once this is complete and the host
MCU clears the I bit, enabling interrupts, the MC68HC705C8 and the JCI are
loaded and ready for multiplex communication. Refer to
graphical representation of the reset sequence.
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
The setup of host MCU RAM
The reset of the JCI
Go to: www.freescale.com
MC68HC705C8/JCI Interface Driver Routines
Figure 9
for a
AN1212/D
17