DSP56F801 Motorola Inc, DSP56F801 Datasheet - Page 45

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DSP56F801

Manufacturer Part Number
DSP56F801
Description
56F801 16-bit Hybrid Controller
Manufacturer
Motorola Inc
Datasheet

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Bypass the V
capacitor such as a tantalum capacitor.
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the V
Take special care to minimize noise levels on the VREF, V
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
DD
and GND circuits.
DD
and V
SS
layers of the PCB with approximately 100 μF, preferably with a high-grade
56F801 Technical Data, Rev. 16
DDA
and V
SSA
pins.
Electrical Design Considerations
45

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