DSP56F801 Motorola Inc, DSP56F801 Datasheet - Page 28

• Manufacturer Part Number: DSP56F801
• Description: 56F801 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

3.5.5
28
External reference crystal frequency for the PLL
PLL output frequency
PLL stabilization time
PLL stabilization time
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
User Manual. ZCLK = f
3. Will not exceed 60MHz for the DSP56F801FA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
Phase Locked Loop Timing
Operating Conditions:
Characteristic
2
4
4
op
0
-40
o
to +85
o
to 0
o
o
C
C
V
56F801 Technical Data, Rev. 16
Table 3-10 PLL Timing
SS
= V
1
SSA
= 0 V, V
Symbol
f
out
f
t
t
osc
plls
plls
DD
/2
= V
DDA
out
Min
40
= 3.0–3.6 V, T
—
—
4
/2, please refer to the OCCS chapter in the
Typ
100
10
—
8
A
= –40° to +85°C
Freescale Semiconductor
Max
200
80
10
—
3
MHz
MHz
Unit
ms
ms