DSP56371D Motorola Inc, DSP56371D Datasheet - Page 21

• Manufacturer Part Number: DSP56371D
• Description: high density CMOS device
• Manufacturer: Motorola Inc

MOTOROLA
Note:
No.
96
97
98
HCKR/HCKT clock cycle
HCKT input rising edge to SCKT output
HCKR input rising edge to SCKR output
1.
2.
3.
4.
5.
6.
7.
8.
V
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
i ck s = internal clock, synchronous mode
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the
bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as
bit length frame sync signal), until the one before last bit clock of the first word in frame.
Periodically sampled and not 100% tested
ESAI_1 specs match those of ESAI_0
Characteristics
CORE_VDD
Table 9 Enhanced Serial Audio Interface Timing (continued)
(asynchronous implies that SCKT and SCKR are two different clocks)
(synchronous implies that SCKT and SCKR are the same clock)
= 1.25 ± 0.05 V; T
Freescale Semiconductor, Inc.
For More Information On This Product,
1, 2, 3
J
DSP56371 Technical Data
Go to: www.freescale.com
= –40°C to 115°C for 150 MHz; T
Symbol
—
—
—
Expression
Enhanced Serial Audio Interface Timing
2 x T
—
—
C
3
J
= 0°C to 100°C for 181 MHz; C
Min
40.0
—
—
Max
18.0
18.0
—
Condition
4
L
= 50 pF
Unit
ns
ns
ns
21