DSP56371D Motorola Inc, DSP56371D Datasheet - Page 17

• Manufacturer Part Number: DSP56371D
• Description: high density CMOS device
• Manufacturer: Motorola Inc

Note:
11.1
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
In I
The programmed serial clock cycle (T
desired SCL serial clock cycle (T
MOTOROLA
No.
60
61
2
C mode, the user may select a value for the programmed serial clock cycle from
HREQ in assertion to first SCL edge
First SCL edge to HREQ in not asserted
(HREQ in hold time.)
1.
where
— HRS is the pr-scaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to
to
•
•
VCORE_VDD = 1.2 5 ± 0.05 V; T
Programming the Serial Clock
divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed.
$FF) may be selected.
Characteristics
I
2
CCP
T
6 × T
4096 × T
I
Table 8 SHI I
is
2
CCP
Freescale Semiconductor, Inc.
C
For More Information On This Product,
= [T
SCL
C
C
), as shown in
(if HDM[7:0] = $02 and HRS = 1)
(if HDM[7:0] = $FF and HRS = 0)
1
× 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
I
I
2
2
CCP
CCP
DSP56371 Technical Data
Go to: www.freescale.com
J
= –40°C to 115°C for 150 MHz; T
2
, is specified by the value of the HDM[7:0] and HRS bits of the
), SCL rise time (T
C Protocol Timing (continued)
Standard I
Table
Serial Host Interface (SHI) I
-0.5
Expression
0.5
Symbol/
T
t
HO;RQI
×
AS;RQI
×
9.
2
T
C*
T
I
C
2
R
CCP
- 21
), should be chosen in order to achieve the
4327
Min
0.0
Standard
J
= 0°C to 100°C for 181 MHz; CL = 50 pF
Max
—
—
2
C Protocol Timing
Fast-Mode
Min
927
0.0
Max
—
—
Unit
ns
ns
17