PDSP16256A Zarlink Semiconductor, PDSP16256A Datasheet - Page 7

• Manufacturer Part Number: PDSP16256A
• Description: Programmable FIR Filter
• Manufacturer: Zarlink Semiconductor

Single Filter Options
When operating as a single filter the device accepts data
on the 16-bit DA bus at the selected sample rate, see
Figs. 5 and 6. Results are presented on the 32-bit F bus,
which may be tristated using the
registered onto the device and does not therefore take
effect until the first SCLK rising edge. Devices may be
cascaded this allows filters with more taps than available
from a single device. To accomplish this two further
buses are utilised. The DB bus presents the input data to
the next device in cascade after the appropriate delay,
while, partial results are accepted on the X bus.
Single filter mode is selected by setting control register bit
15 to a one. The required filter length is then selected
using control register bits 14 and 13 as summarised in
Table 3. The options define the number of times each
multiplier accumulator is used per sample clock period.
This can be once, twice, four times, or eight times.
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible
when the filter coefficients are selected to produce a low
pass filter, since the filtered output would then not contain
14 13 12
0
0
0
0
1
1
1
CR
ACCUMULATE
0 0
0 1
1 0
1 1
0 0
0 1
1 0
EXPANSION
IN
DATA
OUT
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK
SCLK
Table 3 Single Filter options
Input
Rate
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
DELAY LINE
Output
SCLK
Rate
ADDER
DATA
Z
2
1
OEN
COEFF
RAM
128 Taps
128 Taps
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
Length
Filter
input. Signal
Figure. 5 Filter network diagram
DELAY LINE
Latency
ADDER
Setup
DATA
Z
16
17
16
18
20
24
24
2
OEN
1
COEFF
RAM
is
the higher frequency components present in the input.
The Nyquist criterion, specifying that the sampling rate
must be at least double the highest frequency compo-
nent, can still then be satisfied even though the sampling
rate has been halved.
The system clock latency for a single device is shown in
Table 3. This is defined as the delay from a particular data
sample being available on the input pins to the first result
including that input appearing on the output pins. It does
not include the delay needed to gather N samples, for an
N tap filter, before a mathematically correct result is
obtained.
DELAY LINE
ADDER
DATA
Figure. 6 Single Filter bus utilisation
Z
2
1
COEFF
RAM
DB15:0
DA15:0
MUX
NETWORK
NETWORK
PDSP16256/A
SINGLE
A
B
MODE
DELAY LINE
ADDER
X31:0
F31:0
DATA
Z
2
1
OEN
COEFF
MODE
DUAL
RAM
RESULT
DATA
IN
OUT
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