PDSP16256A Zarlink Semiconductor, PDSP16256A Datasheet - Page 15

• Manufacturer Part Number: PDSP16256A
• Description: Programmable FIR Filter
• Manufacturer: Zarlink Semiconductor

PDSP16256 will only transfer the correct number of
coefficients, and one or more significant address bits
will remain low. Sufficient coefficients are always loaded
to allow for a possible Bank Swap to occur, and the
EPROM allocation must allow for this even if the
feature is not to be used. Table 5 shows the number of
coefficients loaded for each of the modes.
If several devices are cascaded, only one device
assumes the role of the Master by having its
grounded. It produces a
vices, plus four higher order address outputs on C15:12,
see Fig. 16. The extra address bits on C15:12 define
separate areas of EPROM, containing coefficients for
up to fifteen additional devices. The least significant
block of memory must always be allocated to the
Master device. The additional devices need not in
practice be all part of the same cascaded chain, but
can consist of several independent filters. They must,
however, all havetheir
still be used to start these independent filters after all
the devices have been loaded. In this case, however,
each slave FEN pin should be driven by DFEN from the
master device.
When one EPROM is supplying information for several
devices, some means of selectively enabling each
additional device must be provided. This is achieved
by using the C11:8 pins on the slave devices as binary
coded inputs to define one to fifteen extra devices.
When the filter length is less than the maximum, the
BYTE
WEN
pins tied low. FRUN can
signal for the other de-
Figure. 17 EPROM Memory Map
EPROM
pin
NOTE:
The EPROM memory map assumes that, for the 32 and 64
coefficient per device options, the unused address pins are
unconnected. If all address pins are connected as shown in
Fig. 16 then the 128 coefficients per device memory map
column should be used. Only those coefficients required will be
read, hence the upper portions of the coefficient address space
will be ignored.
address used for the segment of EPROM allocated to
that device. Code ‘all zeros’ must not be used since the
Master device has implied use of the bottom segment.
This is necessary since the C11:8 pins are alterna-
tively used on the Master device to define the number
of devices supported by the EPROM.
In addition to providing the most significant addresses
to the EPROM, the C15:12 address outputs from the
master device must also drive the C15:12 inputs on the
slave devices. These C15:12 inputs are internally
compared to the C11:8 inputs to decide if that device
is currently to be loaded. This approach avoids the
need for external decoders and makes the
redundant. This input, however, must be tied low on
every device in an EPROM supported system.
The Control Coefficient pin (CCS) is used to define
when the control register is to be loaded. It becomes an
output on the Master device which provides an EPROM
address bit next in significance above A7:0, and also
drives the CCS inputs on the slave devices. This output
is high for the first two EPROM transfers in order to
access the control information, and then remains low
whilst the coefficients are loaded. This control informa-
tion is thus not stored adjacent to the coefficients within
the EPROM, and in fact the EPROM must provide
twice the storage necessary to contain the coefficients
alone. All but two of the bytes in the additional half are
redundant. See Fig.17 for the EPROM memory map.
These coded inputs always correspond to the block
Table 5. Number of coefficients loaded
14 13 12
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Control
Register
Coefficients
Invalid Mode
Number of
PDSP16256/A
Loaded
128
128
128
128
32
64
64
CS
input
15