PDSP16256A Zarlink Semiconductor, PDSP16256A Datasheet - Page 19

• Manufacturer Part Number: PDSP16256A
• Description: Programmable FIR Filter
• Manufacturer: Zarlink Semiconductor

14:13
14:13
14:13
14:13
11:10
11:10
11:10
11:10
Control Register
The internal operation of the PDSP16256 is
controlled by the status of a 16-bit control register. In
the dual filter modes both networks are controlled by
the same register. The significance of the various
bits are shown in Table 6. Tables 7 and 8 define the
control register bit interdependence for the filter and
bank swapping modes.
Bits
9:8
3:0
15
15
12
12
7
7
6
6
5
4
4
Table 6 Control register bit allocation
Decode
00
01
10
11
00
01
10
11
00
0
1
0
1
0
1
0
1
0
1
Dual filter mode
Single filter mode
Sample rate is the system clock
Sample rate is half the system clock
Sample rate is quarter the system
clock
Sample rate is eighth the system clock
Output rate equals the input rate
Decimate-by-two
Intermediate device
Interface device
Termination device
Single device
These bits MUST be at logical zero
Bank swap is controlled by input pin
Bank swap is controlled by Bit 6
Lower bank if bit 7 is set
Upper bank if bit 7 is set
This bit must be at logical zero
Two independent filters
Two filters in cascade
These bits MUST be at logical zero
Function
The control register is double buffered. This allows
the writing of a new control word without affecting the
current operation of the device. To activate the new
control register after it has been written to the device
the bank swap signal must be toggled. After a reset
the active control register is loaded directly and bank
swap need not be used.
X
7
0
1
1
Table 7 Control register filter mode bits
Table 8 Control register bank swap bits
Register
Control
Register
Bits
Control
15
0
0
1
Bits
6
X
0
1
X
X
4
0
1
5
0
0
0
1
Two independent filters
Two filters in cascade
Single Filter
Control by input pin
Lower bank selected
Upper bank selected
Swap on every sample clock
PDSP16256/A
Function
Function
19