PDSP16256A Zarlink Semiconductor, PDSP16256A Datasheet
PDSP16256A
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PDSP16256A Summary of contents
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... PDSP16256/A Programmable FIR Filter DS3709 ISSUE 7.1 Ordering Information Commercial ( +70 C) PDSP16256A/C0/AC 25MHz, PGA package Industrial (- +85 C) PDSP16256 B0/AC 20MHz, PGA package PDSP16256 B0/GC 20MHz, QFP package Military (- +125 C) PDSP16256 MC/AC1R 20MHz, MIL-STD-883* (latest revision), PGA package PDSP16256 MC/GC1R 20MHz, MIL-STD-883* ...
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PDSP16256/A ANALOG INPUT 2 CHANGE EPROM COEFF ADDR DATA POWER-ON RESET RES PDSP INPUT OUTPUT 16256 DATA DATA EPROM SCLK GND Figure dual filter application CHANGE EPROM COEFF ADDR DATA POWER-ON RESET RES COEFFICIENTS PDSP 16256 ADC EPROM ...
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Signal DA15:0 16-bit data input bus to Network A. DB15:0 Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a cascaded chain. Input to Network B in the dual ...
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PDSP16256 Fig. 3a Pin connections for 144 pin PGA package (bottom view) Fig. 3b Pin connections for 172 pin QFP (top view) Figure. 3 Pin connection diagrams (not to scale). See Table 1 for signal descriptions and Table ...
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AC GG Signal GG A15 B15 D13 C14 G15 C15 D14 J15 GND 51 E13 9 F6 ...
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PDSP16256/A SCLK SWAP A7:0 C15:0 CCS WEN COEFFICIENT CS BYTE EPROM FEN DFEN DCLR RES CLKOP Operational Overview The PDSP16256 is an application specific FIR filter for use in high performance digital signal processing systems. Sampling rates can be up ...
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DATA DATA OUT DELAY LINE COEFF ACCUMULATE EXPANSION IN ADDER Single Filter Options When operating as a single filter the device accepts data on the 16-bit DA bus at the selected sample rate, see Figs. 5 and ...
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PDSP16256/A 8 Figure. 7 Single Filter timing diagrams ...
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Dual Indipendant Filter Options When operating as two independent filters the device accepts 16 bit data on both the DA and DB buses at the selected sample rate, see Fig. 8. Results are available from both the F and X ...
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PDSP16256/A Filter Accuary Input data and coefficients are both represented by 16- bit two’s complement numbers. The coefficients are converted to twelve bits by rounding towards zero. This is achieved as follows. If the coefficient is positive then the least ...
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Cascading Devices When the filter requirements are beyond the capabilities of a single device possible to connect several devices in cascade increasing the number of taps avail- able at the required sample rate. Within each device all filter ...
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PDSP16256/A Figure. 13 Full speed cascaded system 12 (a) Single Filters (b) Dual Filters Figure. 14 Coefficient memory map ...
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Filter Control Two control modes are available selected by input signal FRUN. In EPROM load mode, when FRUN is tied high the device will commence operation once the coefficients have been loaded. The CLKOP signal indicates when new input data ...
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PDSP16256/A SCLK 00 A7:0 LOAD MASTER CONTROL REGISTER CCS RES BUSY SCLK A7 CCS C15:12 0000 LOAD LAST LOAD SLAVE 1 MASTER COEFFICIENT Fig. 15b EPROM load sequence for a cascaded system Figure. 15 EPROM load sequence ...
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When the filter length is less than the maximum, the PDSP16256 will only transfer the correct number of coefficients, and one or more significant address bits will remain low. Sufficient coefficients are always loaded to allow for a possible Bank ...
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PDSP16256/A Using a Remote Master When a remote master is used to load coefficients, must be tied high and a EPROM conventional peripheral interface is then provided not possible, however, to read coefficients already stored. The master supplies ...
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SCLK PROCESSOR WRITE STROBE ADDRESS DATA REGISTERED INTO SYNCHRONISATION REGISTER SCLK PROCESSOR WRITE STROBE REGISTERED STROBE PDSP16256 WEN ADDRESS/DATA A7:0/C15:0 Figure. 18 Remote Master synchronisation COEFFICIENT D Q LOAD WEN STATE MACHINE 16256 HOLD A7:0 CIRCUIT C15:0 STROBE STROBE COEFFICIENT ...
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PDSP16256/A 18 Figure. 19 Device startup timing diagrams ...
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Control Register The internal operation of the PDSP16256 is controlled by the status of a 16-bit control register. In the dual filter modes both networks are controlled by the same register. The significance of the various bits are shown in ...
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PDSP16256/A SCLK CCS CS WEN VALID DATA C15:0 VALID ADDRESS A7:0 (a) Coefficient Write Figure. 20 Remote Master setup and hold timings SCLK A7:0 C15:12 CCS C7:0 SCLK OEN F31:0 OUTPUT PINS INPUT PINS 20 SCLK ...
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Electrical Characteristics The Electrical Characteristics are guaranteed over the following range of operating conditions, unless otherwise stated: Commercial to+ AMB IndustriaL - + AMB Military -55 ...
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PDSP16256/A Absolute Maximum Ratings (Note 1) Supply voltage Input voltage Output voltage, V OUT Clamp diode current per pin, I (see note 2) K Static discharge voltage (HBM) Storage temperature Maximum junction temperature, T ...
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Pin Voltage Pin A1 N/C A2 0V/180k A3 0V/180k C10 A4 0V/180k C11 A5 0V/180k C12 A6 0V/180k C13 A7 15·0V C14 A8 0V/180k C15 A9 0V A10 15·0V/180k A11 15·0V/180k A12 15·0V/180k A13 15·0V/180k D13 15·0V/180k A14 D14 A15 ...
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PDSP16256/A Pin Voltage 1 N/C 2 N/C 3 N 5·0V 6 N N/C 10 N/C N N/C 13 N/C 14 N N/C 18 N/C ...
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