IDT72255LA10PF IDT, Integrated Device Technology Inc, IDT72255LA10PF Datasheet - Page 21

IC FIFO SUPERSYNC 8KX18 64QFP

IDT72255LA10PF

Manufacturer Part Number
IDT72255LA10PF
Description
IC FIFO SUPERSYNC 8KX18 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT72255LA10PF

Function
Synchronous
Memory Size
144K (8K x 18)
Access Time
10ns
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
144Kb
Access Time (max)
8ns
Word Size
18b
Organization
8Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4V
Operating Supply Voltage (max)
5.5V
Supply Current
80mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
Not Compliant
Other names
72255LA10PF
800-1499

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72255LA10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72255LA10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72255LA10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72255LA10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Q
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
WCLK
NOTE:
1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.
WCLK
RCLK
0
WEN
procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
REN
PAE
- Q
PAF
OR
1
HF
SI
RT
, W
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
ENS
t
LDS
DS
t
ENS
t
RTS
t
RTS
REF
t
t
LDH
ENH
.
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW4
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
COMMERCIAL AND INDUSTRIAL
3
t
A
t
ENH
t
REF
TEMPERATURE RANGES
(5)
W
1
(4)
BIT X
JANUARY 13, 2009
t
t
LDH
ENH
t
DH
(1)
W
4
2
t
A
4670 drw 16
t
ENH
4670 drw15
W
3

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