IDT72255LA10PF IDT, Integrated Device Technology Inc, IDT72255LA10PF Datasheet
IDT72255LA10PF
Specifications of IDT72255LA10PF
800-1499
Available stocks
Related parts for IDT72255LA10PF
IDT72255LA10PF Summary of contents
Page 1
FEATURES • • • • • Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 • • • • • Pin-compatible with the IDT72275/72285 SuperSync FIFOs • • • • • 10ns read/write ...
Page 2
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DESCRIPTION (CONTINUED) SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data. The input port is controlled ...
Page 3
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DESCRIPTION (CONTINUED) In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A ...
Page 4
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write ...
Page 5
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed ...
Page 6
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10 0°C to +70°C; Industrial: VCC = 5V ± 10 –40°C to +85°C) Symbol Parameter f Clock ...
Page 7
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72255LA/72265LA support two different timing modes of operation: IDT Standard mode or First Word Fall ...
Page 8
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72255LA/72265LA has internal registers for these offsets. Default set- tings are stated in the footnotes of ...
Page 9
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 72255LA — 8,192 x 18–BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, 3FFH HIGH at Master Reset 17 ...
Page 10
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combi- nation of ...
Page 11
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the ...
Page 12
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken ...
Page 13
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device ...
Page 14
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays ...
Page 15
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS ...
Page 16
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS If FWFT = HIGH, ...
Page 17
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN ...
Page 18
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES JANUARY 13, 2009 ...
Page 19
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES JANUARY 13, 2009 ...
Page 20
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 RCLK t t ENS ENH t RTS REN WCLK t RTS WEN t ENS RT EF PAE HF PAF NOTES: ...
Page 21
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. Retransmit ...
Page 22
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 WCLK Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) RCLK NOTE ...
Page 23
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 CLKH CLKL WCLK t t ENH ENS ( words in FIFO (3) n+1 words in FIFO t SKEW2 RCLK 1 NOTES PAE ...
Page 24
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. ...
Page 25
IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72255LA can easily be adapted to applications requiring depths greater than 8,192 and 16,384 for the IDT72265LA with an 18-bit bus width. ...
Page 26
ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns and 20ns speed grades are available as a standard device. 2. Green parts available. For specific speeds and packages contact your sales office. ...
Page 27
VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is ...