IDT72V36110L10PF IDT, Integrated Device Technology Inc, IDT72V36110L10PF Datasheet - Page 28

• Manufacturer Part Number: IDT72V36110L10PF
• Description: IC FIFO SYNC 131KX36 10NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36110L10PF

• Function: Synchronous
• Memory Size: 4.7M (131K x 36)
• Data Rate: 166MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 6.5ns
• Word Size: 36b
• Organization: 128Kx36
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36110L10PF; 800-1530

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
Q
Q0 - Qn
D
D0 - Dn
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
WCLK
WCLK
0
0
RCLK
RCLK
of WCLK and the rising edge of RCLK is less than t
the rising edge of the RCLK and the rising edge of the WCLK is less than t
WEN
SKEW1
WEN
SKEW1
REN
- D
- Q
REN
FF
EF
OE
n
n
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
SKEW1
t
SKEW1
OLZ
t
ENH
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
t
REF
t
A
(1)
t
OE
+ 1*T
t
RCLK
ENH
t
SKEW1
t
ENS
t
A
t
DS
+ t
1
D
(1)
REF.
NO WRITE
0
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
t
SKEW1
t
DH
ENH
LAST WORD
, then EF deassertion may be delayed one extra RCLK cycle.
1
2
t
WFF
t
DS
t
OHZ
TM
t
t
t
CLKH
DS
ENS
36-BIT FIFO
SKEW1
D
D
1
X
NO OPERATION
t
, then the FF deassertion may be delayed one extra WCLK cycle.
WFF
DATA READ
t
t
28
ENH
DH
t
t
DH
CLK
2
t
CLKL
t
t
CLKH
ENS
t
REF
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
REF
2
). If the time between the rising edge
TEMPERATURE RANGES
WFF
NEXT DATA READ
t
t
ENS
OCTOBER 22, 2008
WFF
t
). If the time between
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
6117 drw12
t
DH
t
WFF
6117 drw13
D
1