MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 74

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Reset
Reset
W
R
Hardware Functional Description
* IPbus clock period). If this constraint is violated, new transmissions will be synchronized to the 32 kHz
clock but each 32 kHz clock will not produce a new transmitted data word.
CSRC—Clock source for period counter
WAIT—Number of Clocks Inserted between Data Transactions
7.3.7.7 CSPI Soft Reset Register (RESETREG)
RESETREG is a 32-bit register. Writing a 1 to the START bit resets the CSPI module. All registers in the
CSPI are reset including the CONTROLREG.
START — Soft Reset
7.3.8 Functional Description
7.3.8.1 General
The CSPI module allows full-duplex, synchronous, serial communication between the MC72000 and
peripheral devices. Software can poll the CSPI status flags or CSPI operation can be interrupt-driven.
Figure 43 shows the generic CSPI timing.
74
Table 36 shows WAIT bit field encoding.
The soft reset is extended by two clock cycles so there must be at least three IP_BUS clocks before any
attempt is made to write the CONTROLREG to initiate CSPI operation after the START bit is written.
31
15
0
0
0
1 = 32.68 kHz
0 = Bit clock
1 = Soft reset
0 = No soft reset
30
14
0
0
0
= Unimplemented or Reserved
29
13
0
0
0
28
12
0
0
0
Figure 42. CSPI Soft Reset Register (RESETREG)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
27
11
0
0
0
Register address: Base + 0x1C
0x7FFF
26
10
0x0000
0x0001
0x0002
Table 36. WAIT Encoding
0
0
0
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WAIT
.
.
.
25
0
9
0
0
Preliminary
24
Reserved
0
8
0
0
32768 Clocks
23
0
7
0
0
Function
2 Clocks
0 Clock
1 Clock
.
.
.
22
0
6
0
0
21
0
5
0
0
20
0
4
0
0
19
0
3
0
0
18
0
2
0
0
MOTOROLA
17
0
1
0
0
STAR
16
0
0
0
T
0