MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 122

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Hardware Functional Description
7.4.9 Interrupts
7.4.9.1 General
The SSI can generate four interrupt vectors as shown in Table 25.
7.4.9.2 Description of Interrupt Operation
The following section describes interrupt operation.
7.4.9.2.1
This interrupt can occur when receive interrupts are enabled via the RIE bit of the SCR2 register. When a
data word is ready to transfer from the RXSR to the SRX and the previous SRX data has not yet been read,
the ROE bit is set and the exception interrupt will occur instead of the normal receive data interrupt. An
interrupt will also occur when data is transferred from the RXSR to the RXFIFO with RFF set. In the second
case, data may or may not be lost depending on whether the FIFO has 8 words in it or has been flagged as
full by a watermark.
7.4.9.2.2
This interrupt can occur when receive interrupts are enabled via the RIE bit of the SCR2 register. When a
data word is ready to transfer from the RXSR to the SRX, and the ROE bit is not set, this interrupt will occur
to indicate that received data is available for processing. When the receive FIFO is enabled, this interrupt
will not occur until the receive watermark level of the FIFO is reached. If the FIFO is not enabled, this
interrupt will occur for each data word received.
7.4.9.2.3
This interrupt can occur when transmit interrupts are enabled via the TIE bit of the SCR2 register. When it
is time to transfer data to the TXSR and no data is available in the STX or TXFIFO (if enabled), the TUE
status bit is set and the transmit data exception interrupt occurs.
7.4.9.2.4
This interrupt can occur when transmit interrupts are enabled via the TIE bit of the SCR2 register. When
data is transferred to the TXSR, this interrupt will occur if more data is needed. If the transmit FIFO is not
enabled, this interrupt will occur for each data word transmitted. If the transmit FIFO is enabled, the
interrupt will not occur until the transmit watermark level is reached.
122
Interrupt
INTR+0
INTR+2
INTR+4
INTR+6
INTR+8
Receive Data with Exception
Receive Data
Transmit Data with Exception
Transmit Data
Transmitter
Transmitter
Receiver
Receiver
Receiver
Source
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
Table 62. Interrupt Summary
Receive data with exception
Receive data
Receive last slot interrupt - this interrupt may not be present in all
implementations of the SSI
Transmit data with exception
Transmit data
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Preliminary
Description
MOTOROLA